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HD404889/HD404899/HD404878/ HD404868 Series
Low-Voltage AS Microcomputers with On-Chip LCD Circuit
ADE-202-075D (O) Rev. 5.0 Feb. 2000 Description
The HD404889, HD404899, and HD404868 Series comprise low-voltage, 4-bit single-chip microcomputers with a variety of on-chip supporting functions that include an LCD circuit, A/D converter, multifunctional timers, and large-current I/O pins. These devices are suitable for system and display panel control in a wide range of applications, including pagers, remote controllers, and home appliances equipped with an LCD display. The HD404878 Series comprises low-voltage, 4-bit single-chip microcomputers with no on-chip A/D converter. Each series is equipped with a 32.768 kHz sub-resonator for realtime clock use, providing a time counting facility, and a variety of low-power modes to reduce current drain. The HD4074889, HD4074899, and HD4074869 are ZTATTM microcomputers with on-chip PROM that drastically shortens development time and ensures a smooth transition from debugging to mass production. (The PROM programming specifications are the same as for the 27256 type.) ZTAT TM: Zero Turn-Around Time. ZTAT TM is a trademark of Hitachi, Ltd.
Features
* 46 I/O pins (HD404889/HD404899/HD404878 Series) 41 I/O pins (HD404868 Series) Large-current I/O pins (source: 10 mA max.):4 Large-current I/O pins (sink: 15 mA max.): 8 (HD404889/HD404899/HD404878 Series) 6 (HD404868 Series) LCD segment multiplexed pins:16 Analog input multiplexed pins: 6 (HD404889 and HD404899 Series) 4 (HD404868 Series)
HD404889/HD404899/HD404878/HD404868 Series
* Four Timer/counters 8-bit timer: 2 (HD404889/HD404899/HD404878 Series) 1 (HD404868 Series) 16-bit timer:1 (Can also be used as two 8-bit timer) * 8-bit input capture circuit (HD404889/HD404899/HD404878 Series) * Two timer outputs (including PWM out-put) * Two event counter inputs (edge-programmable) (HD404889/HD404899/HD404878 Series) One event counter input (edge-programmable) (HD404868 Series) * Clock-synchronous 8-bit serial interface * A/D converter 6 channels x 8-bit (HD404889 Series) 6 channels x 10-bit (HD404899 Series) 4 channels x 10-bit (HD404868 Series) * LCD controller/driver (32 segments x 4 commons) (HD404889/HD404899/HD404878 Series) (24 segments x 4 commons) (HD404868 Series) * On-chip oscillators Main clock (ceramic resonator, crystal resonator, or external clock operation possible) Sub-clock (32.768 kHz crystal resonator) * Interrupts External: 3 (including one edge-programmable) Internal : 6 (HD404889 and HD404899 Series) : 5 (HD404878 and HD404868 Series) * Subroutine stack up to 16 levels, including interrupts * Four Low-power dissipation modes * Module standby (timers, serial interface, A/D converter) * System clock division software switching (1/4 or 1/32) * Inputs for return from stop mode (wakeup): 4 * Instruction execution time Min. 0.89 s (fOSC = 4.5 MHz) * Operation voltage 1.8 V to 5.5 V
Cautions about operation!
* Electrical properties presented on the data sheet for the mask ROM and ZTATTM versions will surely and sufficiently satisfy the standard values. However, real capabilities, operation margin, noise margin, and other properties may vary depending on differences of manufacturing processes, internal wiring patterns, etc. Therefore, it is requested for users to carry out an evaluation test for each product on an actual system under the same conditions to see its operation. * Memory register, data area, and stack area values are unstable immediately after power is turned on. They must be initialized before use.
2
HD404889/HD404899/HD404878/HD404868 Series
Ordering Information
HD404889 Series
Type Product Name Model Name HD404888H HD404888TE HD4048812 HD4048812H HD4048812TE HD404889 HD404889H HD404889TE HCD404889 ZTAT
TM
ROM (Words) 8,192
RAM (Digits) 1,344
Package 80-pin plastic QFP (FP-80A) 80-pin plastic TQFP (TFP-80C)
Mask ROM HD404888
12,288
80-pin plastic QFP (FP-80A) 80-pin plastic TQFP (TFP-80C)
16,384
80-pin plastic QFP (FP-80A) 80-pin plastic TQFP (TFP-80C) Chip *2
HCD404889 HD4074889H HD4074889TE 16,384
HD4074889
80-pin plastic QFP*1 (FP-80A) 80-pin plastic TQFP *1 (TFP-80C)
Notes: 1. ZTATTM chip shipment is not supported. 2. The specifications of shipped chips differ from those of the package product. Please contact our sales staff for details.
3
HD404889/HD404899/HD404878/HD404868 Series
HD404899 Series
Type Product Name Model Name HD404898H HD404898TE HD4048912 HD4048912H HD4048912TE HD404899 HD404899H HD404899TE HCD404899 ZTAT
TM
ROM (Words) 8,192
RAM (Digits) 1,344
Package 80-pin plastic QFP (FP-80A) 80-pin plastic TQFP (TFP-80C)
Mask ROM HD404898
12,288
80-pin plastic QFP (FP-80A) 80-pin plastic TQFP (TFP-80C)
16,384
80-pin plastic QFP (FP-80A) 80-pin plastic TQFP (TFP-80C) Chip *2
HCD404899 HD4074899H HD4074899TE 16,384
HD4074899
80-pin plastic QFP*1 (FP-80A) 80-pin plastic TQFP *1 (TFP-80C)
Notes: 1. ZTATTM chip shipment is not supported. 2. The specifications of shipped chips differ from those of the package product. Please contact our sales staff for details. In planning stage.
HD404878 Series
Type Product Name Model Name HD404874H HD404874TE HD404878 HD404878H HD404878TE HCD404878 ZTAT
TM
ROM (Words) 4,096
RAM (Digits) 880
Package 80-pin plastic QFP (FP-80A) 80-pin plastic TQFP (TFP-80C)
Mask ROM HD404874
8,192
80-pin plastic QFP (FP-80A) 80-pin plastic TQFP (TFP-80C) Chip *2
HCD404878
HD4074889 or HD4074899 is used. *1
Notes: 1. ZTATTM chip shipment is not supported. 2. The specifications of shipped chips differ from those of the package product. Please contact our sales staff for details. In planning stage.
4
HD404889/HD404899/HD404878/HD404868 Series
HD404868 Series
Type Product Name Model Name HD404864H HD404864S HD404868 HD404868H HD404868S HCD404868 ZTAT
TM
ROM (Words) 4,096
RAM (Digits) 408
Package 64-pin plastic QFP (FP-64A) 64-pin plastic DILP (DP-64S)
Mask ROM HD404864
8,192
64-pin plastic QFP (FP-64A) 64-pin plastic DILP (DP-64S) Chip *1
HCD404868 HD4074869H HD4074869S 16,384
HD4074869
64-pin plastic QFP (FP-64A) 64-pin plastic DILP (DP-64S)
Note: 1. In planning stage
5
HD404889/HD404899/HD404878/HD404868 Series
List of Functions
Product Name ROM (words) RAM (digit) I/O Large-current I/O pins LCD segment multiplexed pins Analog input multiplexed pins Timer/counter HD404888 8,192 HD4048812 12,288 1,344 46 (max) 4 (source, 10 mA max), 8 (sink, 15 mA max) 16 6 16-bit timer: 1 (Can also be used as two 8-bit timer), 8-bit timer: 2 Input capture Timer output Event input Serial interface A/D converter LCD circuit Interrupt sources External Internal Low-power modes Stop mode Watch mode Standby mode Subactive mode Module standby System clock division software switching Main oscillator Ceramic oscillation Crystal oscillation Sub-oscillator Crystal oscillation 8 bit x 1 2 (PWM output possible) 2 (edge selection possible) 1 (8-bit synchronous) 8 bits x 6 channels Max. 32 seg x 4 com 3 (edge selection possible for 1) 6 4 O O O O O O O O O (32.768kHz) 0.89s(fOSC=4.5MHz) 1.8 to 5.5 80-pin plastic QFP (FP-80A) 80-pin plastic TQFP (TFP-80C) Guaranteed operation temperature(C) -20 to +75 +75 Chip HD404889 HCD404889 16,384
Minimum instruction execution time Operating voltage (V) Package
6
HD404889/HD404899/HD404878/HD404868 Series
Product Name ROM (words) RAM (digit) I/O Large-current I/O pins LCD segment multiplexed pins Analog input multiplexed pins Timer/counter HD4074889 16,384PROM HD404898 8,192 1,344 46 (max) 4 (source, 10 mA max), 8 (sink, 15 mA max) 16 6 16-bit timer: 1 (Can also be used as two 8-bit timer), 8-bit timer: 2 Input capture Timer output Event input Serial interface A/D converter LCD circuit Interrupt sources External Internal Low-power modes Stop mode Watch mode Standby mode Subactive mode Module standby System clock division software switching Main oscillator Ceramic oscillation Crystal oscillation Sub-oscillator Crystal oscillation 8 bits x 6 channels 8 bit x 1 2 (PWM output possible) 2 (edge selection possible) 1 (8-bit synchronous) 10 bits x 6 channels Max. 32 seg x 4 com 3 (edge selection possible for 1) 6 4 O O O O O O O O O (32.768kHz) 0.89s(fOSC=4.5MHz) 2.0 to 5.5 1.8 to 5.5 HD4048912 12,288 HD404899 16,384
Minimum instruction execution time Operating voltage (V) Package Guaranteed operation temperature(C)
80-pin plastic QFP (FP-80A) 80-pin plastic TQFP (TFP-80C) -20 to +75
7
HD404889/HD404899/HD404878/HD404868 Series
Product Name ROM (words) RAM (digit) I/O Large-current I/O pins LCD segment multiplexed pins Analog input multiplexed pins Timer/counter 6 HD40C4899 16,384 HD4074899 16,384PROM 1,344 46 (max) 4 (source, 10 mA max), 8 (sink, 15 mA max) 16 -- HD404874 4,096 880 HD404878 8,192
16-bit timer: 1 (Can also be used as two 8-bit timer), 8-bit timer: 2 8 bit x 1 2 (PWM output possible) 2 (edge selection possible) 1 (8-bit synchronous) 10 bits x 6 channels Max. 32 seg x 4 com External Internal 3 (edge selection possible for 1) 6 4 O O O O O O O O O (32.768kHz) 0.89s(fOSC=4.5MHz) 1.8 to 5.5 Chip 2.0 to 5.5 1.8 to 5.5 5 --
Input capture Timer output Event input Serial interface A/D converter LCD circuit Interrupt sources
Low-power modes Stop mode Watch mode Standby mode Subactive mode Module standby System clock division software switching Main oscillator Ceramic oscillation Crystal oscillation Sub-oscillator Crystal oscillation
Minimum instruction execution time Operating voltage (V) Package
80-pin plastic QFP (FP-80A) 80-pin plastic TQFP (TFP-80C)
Guaranteed operation temperature(C)
+75
-20 to +75
8
HD404889/HD404899/HD404878/HD404868 Series
Product Name ROM (words) RAM (digit) I/O Large-current I/O pins HCD404878 8,192 880 46 (max) 4 (source, 10 mA max), 8 (sink, 15 mA max) -- 16-bit timer: 1 (Can also be used as two 8-bit timer), 8-bit timer: 2 8 bit x 1 2 (edge selection possible) -- HD404864 4,096 408 41 (max) 4 (source, 10 mA max), 6 (sink, 15 mA max) HD404868 8,192 HD4074869 16,384PROM
LCD segment multiplexed pins Analog input multiplexed pins Timer/counter 4
16 16-bit timer: 1 (Can also be used as two 8-bit timer), 8-bit timer: 1
Input capture Timer output Event input
-- 2 (PWM output possible) 1 (edge selection possible)
Serial interface A/D converter LCD circuit Interrupt sources Low-power modes Stop mode Watch mode Standby mode Subactive mode Module standby System clock division software switching Main oscillator Sub-oscillator Ceramic oscillation Crystal oscillation Crystal oscillation 1.8 to 5.5 Chip +75 Minimum instruction execution time Operating voltage (V) Package Guaranteed operation temperature(C) External Internal
1 (8-bit synchronous) 10 bits x 4 channels Max. 32 seg x Max. 24 seg x 4 com 4 com 3 (edge selection possible for 1) 5 4 O O O O O O O O O (32.768kHz) 0.89s(fOSC=4.5MHz) 2.0 to 5.5 64-pin plastic QFP (FP-64A) 64-pin plastic DILP (DP-64S) -20 to +75
9
HD404889/HD404899/HD404878/HD404868 Series
Pin Arrangement
HD404889/HD404899 Series V0 V1 V2 V3 COM4 COM3 COM2 COM1 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 AVcc R70/AN0 R71/AN1 R72/AN2 R73/AN3 R80/AN4 R81/AN5 AVss TEST OSC1 OCS2 GND X2 X1 RESET Vcc D0/INT0 D1/INT1 D2 D3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
FP-80A TFP-80C (Top View)
SEG20 SEG19 SEG18 SEG17 R63/SEG16 R62/SEG15 R61/SEG14 R60/SEG13 R53/SEG12 R52/SEG11 R51/SEG10 R50/SEG9 R43/SEG8 R42/SEG7 R41/SEG6 R40/SEG5 R33/SEG4 R32/SEG3 R31/SEG2 R30/SEG1
10
D4 D5 D6 D7 D8 D9 D10 D11 R00/WU0 R01/WU1 R02/WU2 R03/WU3 R10/EVNB R11/EVND R12/BUZZ R13/TOB R20/TOC R21/SCK R22/SI/SO R23
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
HD404889/HD404899/HD404878/HD404868 Series
HD404878 Series V0 V1 V2 V3 COM4 COM3 COM2 COM1 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 NC R70 R71 R72 R73 R80 R81 NC TEST OSC1 OSC2 GND X2 X1 RESET Vcc D0/INT0 D1/INT1 D2 D3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
FP-80A TFP-80C (Top View)
SEG20 SEG19 SEG18 SEG17 R63/SEG16 R62/SEG15 R61/SEG14 R60/SEG13 R53/SEG12 R52/SEG11 R51/SEG10 R50/SEG9 R43/SEG8 R42/SEG7 R41/SEG6 R40/SEG5 R33/SEG4 R32/SEG3 R31/SEG2 R30/SEG1
D4 D5 D6 D7 D8 D9 D10 D11 R00/WU0 R01/WU1 R02/WU2 R03/WU3 R10/EVNB R11/EVND R12/BUZZ R13/TOB R20/TOC R21/SCK R22/SI/SO R23
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
11
HD404889/HD404899/HD404878/HD404868 Series
V1 V2 V3 COM4 COM3 COM2 COM1 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 R63/SEG16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
HD404868 Series
R70/AN0 R71/AN1 R72/AN2 R73/AN3 TEST OSC1 OSC2 GND X2 X1 RESET Vcc D0/INT0 D1/INT1 D2 D3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
FP-64A (Top View)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
R62/SEG15 R61/SEG14 R60/SEG13 R53/SEG12 R52/SEG11 R51/SEG10 R50/SEG9 R43/SEG8 R42/SEG7 R41/SEG6 R40/SEG5 R33/SEG4 R32/SEG3 R31/SEG2 R30/SEG1 R23
D4 D5 D6 D7 D8 D9 R00/WU0 R01/WU1 R02/WU2 R10/EVNB R11 R12/BUZZ R13/TOB R20/TOC R21/SCK R22/SI/SO
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
COM1 COM2 COM3 COM4 V3 V2 V1 R70/AN0 R71/AN1 R72/AN2 R73/AN3 TEST OSC1 OSC2 GND X2 X1 RESET Vcc D0/INT0 D1/INT1 D2 D3 D4 D5 D6 D7 D8 D9 R00/WU0 R01/WU1 R02/WU2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DP-64S (Top View)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 R63/SEG16 R62/SEG15 R61/SEG14 R60/SEG13 R53/SEG12 R52/SEG11 R51/SEG10 R50/SEG9 R43/SEG8 R42/SEG7 R41/SEG6 R40/SEG5 R33/SEG4 R32/SEG3 R31/SEG2 R30/SEG1 R23 R22/SI/SO R21/SCK R20/TOC R13/TOB R12/BUZZ R11 R10/EVNB
12
HD404889/HD404899/HD404878/HD404868 Series
Pad Arrangement
HCD404889, HCD404899
80
78
76
74
72
70
68
66
64 65 63
79
77
75
73
71
69
67
62 61
1 2 3 4 5 6 7 8
Model Name 60 59 58 57 56 55 54 53
9 10 11 12 13 14 15 16 17 18 19 20 41 43 45 47 49 51
52 50 48 46 44 42
21
23
25
27
29
31
33
35
37 36 38
22
24
26
28
30
32
34
39 Model Name: HD404889 (HCD404889) HD404899 (HCD404899) 40
13
HD404889/HD404899/HD404878/HD404868 Series
Pad Coordinates
HCD404889, HCD404899
Y Chip size (X x Y): Coordinates: Home point position: Pad size (X x Y): Chip thickness: 4.63 x 4.77 (mm) Pad center Chip center 90 x 90 (m) 280 (m)
Mold X Chip center (X=0,Y=0)
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Pad name AV CC R70/AN0 R71/AN1 R72/AN2 R73/AN3 R80/AN4 R81/AN5 AV SS TEST OSC1 OSC2 GND X2 X1 RESETN VCC D0/INT0N D1/INT1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 R00/WU0N R01/WU1N R02/WU2N R03/WU3N R10/EVNB R11/EVND R12/BUZZ R13/TOB R20/TOC R21/SCKN R22/Si/SO R23
Coodinates X (m) -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -2129 -1677 -1506 -1335 -1163 -992 -821 -649 -478 -307 -135 36 208 379 550 722 893 1064 1236 1407 1588
Y (m) 1779 1589 1417 1246 1074 903 732 506 103 -68 -240 -434 -605 -776 -948 -1119 -1290 -1462 -1633 -1804 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199 -2199
Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Pad name R30/SEG1 R31/SEG2 R32/SEG3 R33/SEG4 R40/SEG5 R41/SEG6 R42/SEG7 R43/SEG8 R50/SEG9 R51/SE10 R52/SEG11 R53/SEG12 R60/SEG13 R61/SEG14 R62/SEG15 R63/SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 COM1 COM2 COM3 COM4 V3 V2 V1 V0
Coodinates X (m) 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 2129 1588 1407 1236 1064 893 722 550 379 208 36 -135 -307 -478 -649 -821 -992 -1163 -1335 -1506 -1677
Y (m) -1787 -1616 -1445 -1273 -1102 -973 -759 -588 -417 -245 -74 98 269 440 612 783 954 1126 1297 1477 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199 2199
14
HD404889/HD404899/HD404878/HD404868 Series
Pad Arrangement
HCD404878
78
76
74
72
70
68
66
64
62 63 61
77
75
73
71
69
67
65
60 59
Model Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 41 40 39 43 42 45 44 47 46 49 48 51 50 53 52 55 54 57 56 58
19
21
23
25
27
29
31
33
35 34 36
20
22
24
26
28
30
32
37 38
Model Name: HD404878 (HCD404878)
15
HD404889/HD404899/HD404878/HD404868 Series
Pad Coordinates
HCD404878
Y Chip size (X x Y): Coordinates: Home point position: Pad size (X x Y): Chip thickness: 4.13 x 4.26 (mm) Pad center Chip center 90 x 90 (m) 280 (m)
Mold X Chip center (X=0,Y=0)
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Pad name R70 R71 R72 R73 R80 R81 TEST OSC1 OSC2 GND X2 X1 RESETN VCC D0/INT0N D1/INT1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 R00/WU0N R01/WU1N R02/WU2N R03/WU3N R10/EVNB R11/EVND R12/BUZZ R13/TOB R20/TOC R21/SCKN R22/Si/SO R23 R30/SEG1
Coodinates X (m) -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1879 -1654 -1488 -1322 -1155 -989 -823 -656 -490 -324 -158 9 175 341 508 674 840 1007 1173 1339 1506 1879
Y (m) 1446 1280 1114 948 781 615 449 282 116 -73 -239 -406 -572 -738 -905 -1071 -1237 -1404 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1943 -1571
Pad No. 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
Pad name R31/SEG2 R32/SEG3 R33/SEG4 R40/SEG5 R41/SEG6 R42/SEG7 R43/SEG8 R50/SEG9 R51/SE10 R52/SEG11 R53/SEG12 R60/SEG13 R61/SEG14 R62/SEG15 R63/SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 COM1 COM2 COM3 COM4 V3 V2 V1 V0
Coodinates X (m) 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1879 1509 1351 1192 1033 874 716 557 398 239 81 -78 -237 -411 -570 -728 -887 -1038 -1194 -1351 -1507
Y (m) -1405 -1239 -1072 -906 -740 -573 -407 -241 -74 92 258 425 591 757 924 1087 1246 1405 1564 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943 1943
16
HD404889/HD404899/HD404878/HD404868 Series
Pin Description
HD404889/HD404899/HD404878 Series
Pin Number Item Power supply Test Reset Oscillation Symbol VCC GND TEST RESET OSC1 OSC2 X1 X2 Port D0-D11 FP-80A TFP-80C 16 12 9 15 10 11 14 13 17-28 I/O -- -- Input Input Input Output Input Output I/O Function Apply the power supply voltage to this pin. Connect to ground. Not for use by the user application. Connect to GND potential. Used to reset the MCU. Internal oscillator input/output pins. Connect a ceramic resonator, crystal resonator, or external oscillator circuit. Realtime clock oscillator input/output pins. Connect a 32.768 kHz crystal. If 32.768 kHz crystal oscillation is not used, fix the x1 pin to VCC and leave the x2 pin open. I/O pins addressed bit by bit. D 0 to D3 are large-current source pins (max. 10 mA), and D4 to D11 are largecurrent sink pins (max. 15 mA). I/O pins, addressed in 4-bit units. External interrupt input pins Input pins used for transition from stop mode to active mode. Serial interface clock I/O pin Serial interface receive data input pin Serial interface transmit data output pin Timer output pins Event count input pins LCD driver power supply pins. The on-chip power supply dividing resistor can be disconnected by software. Power supply conditions are: VCCV1V 2V 3GND. LCD common signal pins LCD segment signal pins A/D converter power supply pin. Connect as close as possible to the VCC pin so as to be at the same potential as VCC. Ground pin for AVCC. Connect as close as possible to the GND pin so as to be at the same potential as GND. A/D converter analog input pins Timer overflow toggle output or divided system clock output pin Connect to ground potential.
R00-R6 3 R70-R8 1 Interrupt Wakeup Serial interface INT0,INT1 WU0-WU3 SCK SI SO Timer LCD TOB,TOC EVNB,EVND V0-V3
29-56, 2-7 17,18 29-32 38 39 39 36,37 33,34 80-77
I/O Input Input I/O Input Output Output Input --
COM1-COM4 SEG1-SEG32 A/D converter
*1
73-76 41-72 1
Output Output --
AV CC
AV SS AN0-AN 5 Buzzer output Other BUZZ NC
8 2-7 35 1, 8*2
-- Input Output --
Notes: 1. Applies to HD404889 and HD404899 series. 2. Applies to HD404878 series.
17
HD404889/HD404899/HD404878/HD404868 Series
HD404868 Series
Pin Number FP-64A Item Power supply Test Reset Oscillation Symbol VCC GND TEST RESET OSC1 OSC2 X1 X2 Port D0-D9 12 8 5 11 6 7 10 9 13-22 19 15 12 18 13 14 17 16 20-29 DP-64S I/O -- -- Input Input Input Function Apply the power supply voltage to this pin. Connect to ground. Not for use by the user application. Connect to GND potential. Used to reset the MCU.
Internal oscillator input/output pins. Connect a ceramic resonator, crystal resonator, or external Output oscillator circuit. Input Realtime clock oscillator input/output pins. Connect a 32.768 kHz crystal. If 32.768 kHz is Output crystal oscillation pinnot used, fix the x1 pin to VCC and leave the x2 open. I/O I/O pins addressed bit by bit. D 0 to D3 are largecurrent source pins (max. 10 mA), and D4 to D9 are large-current sink pins (max. 15 mA). I/O pins, addressed in 4-bit units.
R00-R0 2 R10-R6 3 R70-R7 3 Interrupt Wakeup Serial interface INT0,INT1 WU0-WU2 SCK SI SO Timer LCD TOB,TOC EVNB V1-V3
23-25 26-49 1-4 13,14 23-25 31 32 32 29, 30 26 64-62
30-32 33-56 8-11 20, 21 30-32 38 39 39 36, 37 33 7-5
I/O
Input Input I/O Input
External interrupt input pins Input pins used for transition from stop mode to active mode. Serial interface clock I/O pin Serial interface receive data input pin
Output Serial interface transmit data output pin Output Timer output pins Input -- Event count input pins LCD driver power supply pins. The on-chip power supply dividing resistor can be disconnected by software. Power supply conditions are: VCCV1V 2V 3GND.
COM1-COM4 SEG1-SEG24 A/D converter Buzzer output AN0-AN 3 BUZZ
58-61 34-57 1-4 28
1-4 41-64 8-11 35
Output LCD common signal pins Output LCD segment signal pins Input A/D converter analog input pins Output Timer overflow toggle output or divided system clock output pin
18
HD404889/HD404899/HD404878/HD404868 Series
Block DiagramG
HD404889/HD404899 Series
RESET TEST OSC1 OSC2 X1 X2 Vcc GND WU0 WU1 WU2 WU3
HMCS400 CPU
ROM
RAM
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 R30 R31 R32 R33 R40 R41 R42 R43 R50 R51 R52 R53 R60 R61 R62 R63 R70 R71 R72 R73 R80 R81
P-MOS largecurrent buffer
D Port
N-MOS largecurrent buffer
TOB 8-bit timer B EVNB
TOC
8-bit timer C
EVND
8-bit timer D
SCK SI/SO AVcc AN0 AN1 AN2 AN3 AN4 AN5 AVss SEG1 to SEG32 COM1 to COM4 V0 V1 V2 V3 BUZZ
Synchronous serial interface
Buzzer output circuit
: Data bus
R8 Port
LCD circuit 32-segment x 4 common
R7 Port
R6 Port
A/D converter 8-bit x 6 channels (HD404889 Series) 10-bit x 6 channels (HD404899 Series)
R5 Port
R4 Port
R3 Port
R2 Port
R1 Port
8-bit timer A
R0 Port
INT0 INT1
External interrupt control circuit
: Signal line
19
HD404889/HD404899/HD404878/HD404868 Series
HD404878 Series
RESET TEST OSC1 OSC2 X1 X2 Vcc GND WU0 WU1 WU2 WU3
HMCS400 CPU
ROM
RAM
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 R30 R31 R32 R33 R40 R41 R42 R43 R50 R51 R52 R53 R60 R61 R62 R63 R70 R71 R72 R73 R80 R81
P-MOS largecurrent buffer
D Port
N-MOS largecurrent buffer
TOB 8-bit timer B EVNB
TOC
8-bit timer C
EVND
8-bit timer D
SCK SI/SO
Clock-synchronous 8-bit serial interface
SEG1 to SEG32 COM1 to COM4 V0 V1 V2 V3 BUZZ
Buzzer output circuit
: Data bus
R8 Port
LCD circuit 32-segment x 4 common
R7 Port
R6 Port
R5 Port
R4 Port
R3 Port
R2 Port
R1 Port
8-bit timer A
R0 Port
INT0 INT1
External interrupt control circuit
: Signal line
20
HD404889/HD404899/HD404878/HD404868 Series
HD404868 Series
RESET TEST OSC1 OSC2 X1 X2 VCC GND WU0 WU1 WU2
HMCS400 CPU
ROM
RAM
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
P-MOS largecurrent buffer
D Port
N-MOS largecurrent buffer
R0 Port
INT0 INT1
External interrupt control circuit
R00 R01 R02 R10 R11 R12 R13
8-bit timer A R1 Port
EVNB TOB
8-bit timer B
TOC
8-bit timer C
R20 R21 R22 R23 R30 R31 R32 R33
Clock-synchronous 8-bit serial interface
AN0 AN1 AN2 AN3
R3 Port
SCK SI/SO
R2 Port
A/D converter 4 channels x 10-bit
R40 R41 R42 R43
R4 Port
SEG1
R50 R51 R52 R53
SEG24 COM1 COM4 V1 V2 V3
R5 Port
~
R6 Port Buzzer output circuit R7 Port
BUZZ
~ ~
~
LCD circuit 24-segment x 4 common
R60 R61 R62 R63 R70 R71 R72 R73
21
HD404889/HD404899/HD404878/HD404868 Series
Memory Map
ROM Memory Map The ROM memory map is shown in figure 1 and is described below. Vector address area ($0000 to $000F): When an MCU reset or interrupt handling is performed, the program is executed from the vector address. A JMPL instruction should be used to branch to the start address of the reset routine or the interrupt routine. Zero page subroutine area ($0000 to $003F):A branch can be made to a subroutine in the area $0000 to $003F with the CAL instruction. Pattern area ($0000 to $0FFF): ROM data in the area $0000 to $0FFF can be referenced as pattern data with the P instruction. Program area ($0000 to $0FFF(HD404874, HD404864)), ($0000 to $1FFF (HD404888, HD404898, HD404878, HD404868, HCD404878)), ($0000 to $2FFF (HD4048812, HD4048912)), ($0000 to $3FFF (HD404889, HD404899, HCD404889, HCD404899, HD4074899, HD4074889, HD4074869))
22
HD404889/HD404899/HD404878/HD404868 Series
$0000 $000F Zero page subroutine area (64 words) $003F HD404874/HD404864 pattern/program area (4,096 words) Vector addresses (16 words) $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $0FFF $000A $000B HD404888/HD404898/HD404878/ HD404868/HCD404878 pattern/program area (8,192 words) $1FFF $000C $000D $000E $000F JMPL instruction (Jump to reset routine) JMPL instruction (Jump to WU0 to WU3 routine) JMPL instruction (Jump to INT0 routine) JMPL instruction (Jump to INT1 routine) JMPL instruction (Jump to timer A routine) JMPL instruction (Jump to timer B/timer D routine) JMPL instruction (Jump to timer C routine) JMPL instruction (Jump to A/D or serial interface routine)
HD4048812/HD4048912 pattern/program area (12,288 words)
$2FFF HD404889/HD4074889/ HD404899/HD4074899/HD4074869/ HCD404889/HCD404899 pattern/program area (16,384 words) $3FFF
Figure 1 ROM Memory Map RAM Memory Map The MCU has on-chip RAM comprising a memory register area, LCD data area, data area, and stack area. In addition to these areas, an interrupt control bit area, special register area, and register flag area are mapped onto RAM memory space as a RAM-mapped register area.The RAM memory map is shown in figure 2 and described below. Memory register, LCD data area, data area, and stack area values are unstable immediately after power is turned on. They must be initialized before use.
23
HD404889/HD404899/HD404878/HD404868 Series
HD404889 Series
$000 $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F
Interrupt control bit area Speed Select Reg. (SSR) Miscellaneous Reg. (MIS) Edge Select Reg. (ESR) Not used Port Mode Reg.0 (PMR0) Port Mode Reg.1 (PMR1) Port Mode Reg.2 (PMR2) Port Mode Reg.3 (PMR3) Port Mode Reg.4 (PMR4) Module Standby Reg.1 (MSR1) Module Standby Reg.2 (MSR2) Timer Mode Reg.A (TMA) Timer Mode Reg.B1 (TMB1) Timer Mode Reg.B2 (TMB2) (TRBL/TWBL) Timer-B (TRBU/TWBU) Timer Mode Reg.C1 (TMC1) Timer Mode Reg.C2 (TMC2) (TRCL/TWCL) Timer-C (TRCU/TWCU) Timer Mode Reg.D1 (TMD1) Timer Mode Reg.D2 (TMD2) (TRDL/TWDL) Timer-D (TRDU/TWDU) Not used W W W W W W W W W W W W W R/W R/W W W R/W R/W W W R/W R/W
RAM-mapped register area
$03F $040 $04F $050
Memory register (MR) area (16 digits) LCD data area (32 digits)
$06F $070 Not used $08F $090
* *
Data (464 digits) V = 0 (bank = 0)
Data (464 digits) V = 1 (bank = 1)
Register flag area Serial Mode Reg.1 Serial Mode Reg.2 Serial Data Reg.Lower Serial Data Reg.Upper A/D Mode reg. Not used A/D Data Reg.Lower A/D Data Reg.Upper LCD Control Reg. LCD Mode Reg. Buzzer Mode Reg. Not used Port D0~D3 DCR Port D4~D7 DCR Port D8~D11 DCR Not used Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Port R4 DCR Port R5 DCR Port R6 DCR Port R7 DCR Port R8 DCR Not used Vreg. (V) R/W (SMR1) W (SMR2) W (SRL) R/W (SRU) R/W (AMR) W (ADRL) (ADRU) (LCR) (LMR) (BMR) (DCD0) (DCD1) (DCD2) (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR5) (DCR6) (DCR7) (DCR8) R R W W W W W W W W W W W W W W W
$25F $260
Data (304 digits)
$38F $390 Not used $3BF $3C0
Stack area (64 digits) $3FF
Notes: R W
: Read : Write
$012 $013 $016 $017 $01A $01B
Timer Read Reg.B Lower Timer Read Reg.B Upper Timer Read Reg.C Lower Timer Read Reg.C Upper Timer Read Reg.D Lower Timer Read Reg.D Upper
(TRBL) (TRBU) (TRCL) (TRCU) (TRDL) (TRDU)
R R R R R R
Timer Write Reg.B Lower Timer Write Reg.B Upper Timer Write Reg.C Lower Timer Write Reg.C Upper Timer Write Reg.D Lower Timer Write Reg.D Upper
(TWBL) W (TWBU) W (TWCL) W (TWCU) W (TWDL) W (TWDU) W
R/W : Read/Write *Two registers are mapped onto the same address ($012, $013, $016, $017, $01A, $01B).
Figure 2 RAM Memory Map
24
HD404889/HD404899/HD404878/HD404868 Series
HD404899 Series
$000 $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F
Interrupt control bit area Speed Select Reg. (SSR) Miscellaneous Reg. (MIS) Edge Select Reg. (ESR) Not used Port Mode Reg.0 (PMR0) Port Mode Reg.1 (PMR1) Port Mode Reg.2 (PMR2) Port Mode Reg.3 (PMR3) Port Mode Reg.4 (PMR4) Module Standby Reg.1 (MSR1) Module Standby Reg.2 (MSR2) Timer Mode Reg.A (TMA) Timer Mode Reg.B1 (TMB1) Timer Mode Reg.B2 (TMB2) (TRBL/TWBL) Timer-B (TRBU/TWBU) Timer Mode Reg.C1 (TMC1) Timer Mode Reg.C2 (TMC2) (TRCL/TWCL) Timer-C (TRCU/TWCU) Timer Mode Reg.D1 (TMD1) Timer Mode Reg.D2 (TMD2) (TRDL/TWDL) Timer-D (TRDU/TWDU) Not used W W W W W W W W W W W W W R/W R/W W W R/W R/W W W R/W R/W
RAM-mapped register area
$03F $040 $04F $050
Memory register (MR) area (16 digits) LCD data area (32 digits)
$06F $070 Not used $08F $090
*
Data (464 digits) V = 0 (bank = 0)
Data (464 digits) V = 1 (bank = 1)
Register flag area Serial Mode Reg.1 Serial Mode Reg.2 Serial Data Reg.Lower Serial Data Reg.Upper A/D Mode reg. A/D Data Reg.Lower A/D Data Reg.Middle A/D Data Reg.Upper LCD Control Reg. LCD Mode Reg. Buzzer Mode Reg. Not used Port D0~D3 DCR Port D4~D7 DCR Port D8~D11 DCR Not used Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Port R4 DCR Port R5 DCR Port R6 DCR Port R7 DCR Port R8 DCR Not used Vreg. (V) R/W (SMR1) W (SMR2) W (SRL) R/W (SRU) R/W (AMR) W (ADRL) R (ADRM) R (ADRU) R (LCR) W (LMR) W (BMR) W (DCD0) (DCD1) (DCD2) (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR5) (DCR6) (DCR7) (DCR8) W W W W W W W W W W W W
$25F $260
Data (304 digits)
$38F $390 Not used $3BF $3C0
Stack area (64 digits)
$3FF
Notes: R W
: Read : Write
$012 $013 $016 $017 $01A $01B
Timer Read Reg.B Lower Timer Read Reg.B Upper Timer Read Reg.C Lower Timer Read Reg.C Upper Timer Read Reg.D Lower Timer Read Reg.D Upper
(TRBL) (TRBU) (TRCL) (TRCU) (TRDL) (TRDU)
R R R R R R
Timer Write Reg.B Lower Timer Write Reg.B Upper Timer Write Reg.C Lower Timer Write Reg.C Upper Timer Write Reg.D Lower Timer Write Reg.D Upper
(TWBL) W (TWBU) W (TWCL) W (TWCU) W (TWDL) W (TWDU) W
R/W : Read/Write *Two registers are mapped onto the same address ($012, $013, $016, $017, $01A, $01B).
Figure 2 RAM Memory Map (cont)
25
HD404889/HD404899/HD404878/HD404868 Series
HD404878 Series
$000 $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F
Interrupt control bit area Speed Select Reg. (SSR) Miscellaneous Reg. (MIS) Edge Select Reg. (ESR) Not used Port Mode Reg.0 (PMR0) Port Mode Reg.1 (PMR1) Port Mode Reg.2 (PMR2) Port Mode Reg.3 (PMR3) Port Mode Reg.4 (PMR4) Module Standby Reg.1 (MSR1) Module Standby Reg.2 (MSR2) Timer Mode Reg.A (TMA) Timer Mode Reg.B1 (TMB1) Timer Mode Reg.B2 (TMB2) (TRBL/TWBL) Timer-B (TRBU/TWBU) Timer Mode Reg.C1 (TMC1) Timer Mode Reg.C2 (TMC2) (TRCL/TWCL) Timer-C (TRCU/TWCU) Timer Mode Reg.D1 (TMD1) Timer Mode Reg.D2 (TMD2) (TRDL/TWDL) Timer-D (TRDU/TWDU) Not used W W W W W W W W W W W W W R/W R/W W W R/W R/W W W R/W R/W
RAM-mapped register area
$03F $040 $04F $050
Memory register (MR) area (16 digits) LCD data area
$06F $070
(32 digits) Not used
$08F $090
*
Data (768 digits)
Register flag area Serial Mode Reg.1 Serial Mode Reg.2 Serial Data Reg.Lower Serial Data Reg.Upper Not used LCD Control Reg. LCD Mode Reg. Buzzer Mode Reg. Not used Port D0~D3 DCR Port D4~D7 DCR Port D8~D11 DCR Not used Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Port R4 DCR Port R5 DCR Port R6 DCR Port R7 DCR Port R8 DCR Not used (LCR) (LMR) (BMR) (DCD0) (DCD1) (DCD2) (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR5) (DCR6) (DCR7) (DCR8) W W W W W W W W W W W W W W W (SMR1) W (SMR2) W (SRL) R/W (SRU) R/W
$38F $390 Not used $3BF $3C0
Stack area (64 digits)
$3FF
Notes: R W
: Read : Write
$012 $013 $016 $017 $01A $01B
Timer Read Reg.B Lower Timer Read Reg.B Upper Timer Read Reg.C Lower Timer Read Reg.C Upper Timer Read Reg.D Lower Timer Read Reg.D Upper
(TRBL) (TRBU) (TRCL) (TRCU) (TRDL) (TRDU)
R R R R R R
Timer Write Reg.B Lower Timer Write Reg.B Upper Timer Write Reg.C Lower Timer Write Reg.C Upper Timer Write Reg.D Lower Timer Write Reg.D Upper
(TWBL) W (TWBU) W (TWCL) W (TWCU) W (TWDL) W (TWDU) W
R/W : Read/Write *Two registers are mapped onto the same address ($012, $013, $016, $017, $01A, $01B).
Figure 2 RAM Memory Map (cont)
26
HD404889/HD404899/HD404878/HD404868 Series
HD404868 Series
$000 $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F Interrupt control bit area Speed Select Reg. Miscellaneous Reg. Edge Select Reg. Not used Port Mode Reg.0 Port Mode Reg.1 Port Mode Reg.2 Port Mode Reg.3 Port Mode Reg.4 Module Standby Reg.1 Module Standby Reg.2 Timer Mode Reg.A Timer Mode Reg.B1 Timer Mode Reg.B2 Timer B Timer Mode Reg.C1 Timer Mode Reg.C2 Timer C (SSR) W (MIS) W (ESR) W (PMR0) (PMR1) (PMR2) (PMR3) (PMR4) (MSR1) (MSR2) (TMA) (TMB1) (TMB2) (TRBL/TWBL) (TRBU/TWBU) (TMC1) (TMC2) (TRCL/TWCL) (TRCU/TWCU) W W W W W W W W W W R/W R/W W W R/W R/W
RAM-mapped register area
$03F $040 Memory register (MR) area (16 digits) $04F $050 LCD data area (24 digits) $067 $068 Not used $08F $090
*
Data (304 digits)
Not used
Register flag area Serial Mode Reg.1 Serial Mode Reg.2 Serial Mode Reg.Lower Serial Mode Reg.Upper A/D Mode reg. A/D Data Reg.Lower A/D Data Reg.Middle A/D Data Reg.Upper LCD Control Reg. LCD Mode Reg. Buzzer Mode Reg. Not used Port D0-D3 DCR Port D4-D7 DCR Port D8-D9 DCR Not used Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Port R4 DCR Port R5 DCR Port R6 DCR Port R7 DCR (SMR1) (SMR2) (SRL) (SRU) (AMR) (ADRL) (ADRM) (ADRU) (LCR) (LMR) (BMR) W W R/W R/W W R R R W W W
$1BF $1C0
Not used
(DCD0) W (DCD1) W (DCD2) W (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR5) (DCR6) (DCR7) W W W W W W W W
$3BF $3C0
Stack area (64 digits)
Not used
$3FF
Notes:
R : Read W : Write R/W: Read/Write *Two registers are mapped onto the same address ($012, $013, $016, $017).
$012 $013 $016 $017
Timer Read Reg.B Lower Timer Read Reg.B Upper Timer Read Reg.C Lower Timer Read Reg.C Upper
(TRBL) (TRBU) (TRCL) (TRCU)
R R R R
Timer Write Reg.B Lower Timer Write Reg.B Upper Timer Write Reg.C Lower Timer Write Reg.C Upper
(TWBL) (TWBU) (TWCL) (TWCU)
W W W W
Figure 2 RAM Memory Map (cont)
27
HD404889/HD404899/HD404878/HD404868 Series
RAM-mapped register area ($000 to $03F): * Interrupt control bit area ($000 to $003) This area consists of bits used for interrupt control. Its configuration is shown in figure 3. Individual bits can only be accessed by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, TM/TMD). There are restrictions on access to certain bits. The individual bits and instruction restrictions are shown in figure 4. * Special register area ($004 to $01F, $024 to $03F) This area comprises mode registers and data registers for external interrupts, the serial interface, timers, LCD, A/D converter, etc., and I/O pin data control registers. Its configuration is shown in figures 2 and 5. These registers are of three kinds: write-only (W), read-only (R), and read/write (R/W). The SEM/SEMD and REM/REMD instructions can be used on the LCD control register (LCR: $02C) and the third bit of buzzer mode register (BMR3: $02E, 3), but RAM bit manipulation instructions cannot be used on the other registers. * Register flag area ($020 to $023) This area consists of the DTON and WDON flags and interrupt control bits. Its configuration is shown in figure 3. Individual bits can only be accessed by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, TM/TMD). There are restrictions on access to certain bits. The individual bits and instruction restrictions are shown in figure 4. Memory register (MR) area ($040 to $04F): In this data area, the 16 memory register digits (MR(0) to MR(15)) can also be accessed by the registerregister instructions LAMR and XMRA. The configuration of this area is shown in figure 6. LCD data area: $050 to $06F (HD404889/HD404899/HD404878 Series) $050 to $067 (HD404868 Series) This 32-digit data area stores data to be displayed on an LCD. Data written in this area is automatically outputed to segments as display data. "1" data indicates "on" and "0" data "off" (see the section of the LCD circuit for details). Data area: $090 to $38F (HD404889/HD404899/HD404878 Series) $090 to $1BF (HD404868 Series) For the 464 digits from $090 to $25F, the bank can be switched according to the value of the bank register (V: $03F) (figure 7). The bank register value must always be set when accessing the area from $090 to $25F. The data area from $260 to $38F can be addressed without a bank register setting. Stack area ($3C0 to $3FF): This is the stack area used to save the contents of the program counter (PC), status flag (ST), and carry flag (CA) when a subroutine call (CAL or CALL instruction) or interrupt handling is performed. As four digits are used for one level, the area can be used as a subroutine stack with a maximum of 16 levels. The saved data and saved status information are shown in figure 6. The program counter is restored by the RTN and RTNI instructions. The status and carry flags are restored by the RTNI instruction, but are not affected by the RTN instruction. Any part of the area not used for saving can be used as a data area.
28
HD404889/HD404899/HD404878/HD404868 Series
RAM address $000 Bit 3 IMWU*1 (WU0 to WU3 interrupt mask) IM1 (INT1 interrupt mask) IMTB (Timer B interrupt mask) IMAD*3 (A/D converter interrupt mask) Bit 2 IFWU*2 (WU0 to WU3 interrupt request flag) IF1 (INT1 interrupt request flag) IFTB (Timer B interrupt request flag) IFAD*3 (A/D converter interrupt request flag) Bit 1 RSP (Stack pointer reset) IM0 (INT0 interrupt mask) IMTA (Timer A interrupt mask) IMTC (Timer C interrupt mask) Bit 0 IE (Interrupt enable flag) IF0 (INT0 interrupt request flag) IFTA (Timer A interrupt request flag) IFTC (Timer C interrupt request flag)
$001
$002
$003
$020
DTON (DTON flag) GEF (Gear enable flag) IMTD*4 (Timer D interrupt mask) IMS (Serial interrupt mask) IF IM IE SP
ADSF*3 (A/D start flag) Not used IFTD*4 (Timer D interrupt request flag) IFS (Serial interrupt request flag)
WDON (Watchdog on flag) ICEF (Input capture error flag) Not used
LSON (Low speed on flag) ICSF (Input capture status flag) Not used
$021
$022
$023
Not used
Not used
: Interrupt Request Flag : Interrupt Mask : Interrupt Enable Flag : Stack Pointer
Notes: 1. WU0 to WU2 interrupt mask in the HD404868 Series 2. WU0 to WU2 interrupt request flag in the HD404868 Series 3. Applies to the HD404889, HD404899, and HD404868 Series. 4. Applies to the HD404889, HD404899, and HD404878 Series.
Figure 3 Interrupt Control Bit and Register Flag Area Configuration
29
HD404889/HD404899/HD404878/HD404868 Series
Bits in the interrupt control bit area and register flag area can be set and reset by the SEM or SEMD instruction and the REM or REMD instruction, and tested by the TM or TMD instruction. They are not affected by any other instructions. The following restrictions apply to individual bits. SEM/SEMD IE IM LSON IF ICSF ICEF GEF RSP WDON ADSF* DTON Not Used Allowed Not executed Allowed Allowed Not executed in active mode Used in subactive mode Not executed Allowed Allowed Not executed Inhibited Allowed Not executed Inhibited Inhibited Inhibited Allowed Allowed Inhibited Not executed Allowed Allowed Allowed Allowed Allowed REM/REMD TM/TMD
Notes : The WDON bit is reset only by stop mode clearance by means of an MCU reset. Do not use the REM or REMD instruction on the ADSF bit during A/D conversion. The DTON bit is always in the reset state in active mode. If the TM or TMD instruction is used on a bit for which its use is prohibited, or on a nonexistent bit, the status flag value will be undetermined. * Applies to HD404889, HD404899, and HD404868 Series.
Figure 4 Instruction Restrictions
30
HD404889/HD404899/HD404878/HD404868 Series
HD404889 Series
RAM address Bit 3 Bit 2 Bit 1 Bit 0
SSR MIS ESR PMR0 PMR1 PMR2 PMR3 PMR4 MSR1 MSR2 TMA TMB1 TMB2 TRBL/TWBL TRBU/TWBU TMC1 TMC2 TRCL/TWCL TRCU/TWCU TMD1 TMD2 TRDL/TWDL TRDU/TWDU
SMR1 SMR2 SRL SRU AMR ADRL ADRU LCR LMR BMR DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR5 DCR6 DCR7 DCR8
V
$000 Interrupt control bit area $003 System clock frequency 32 kHz oscillation stop setting 32 kHz frequency division System clock selection $004 division ratio switching ratio selection Interrupt frame period selection Not used $005 Pull-up MOS control Not used INT1 edge detection selection $006 Not used $007 Not used D1/INT1 D0/INT0 $008 $009 R03/WU3 R02/WU2 R01/WU1 R00/WU0 R13/TOB R12/BUZZ R11/EVND R10/EVNB $00A $00B R20/TOC R22/SI/SO R21/SCK R5/SEG9~12 R4/SEG5~8 R3/SEG1~4 $00C R6/SEG13~16 Not used Timer B lock on/off Timer D clock on/off Timer C clock on/off $00D Serial clock on/off A/D clock on/off Not used $00E $00F TimerA/Timer base Timer A clock source selection Reload on/off Timer B clock source selection $010 Timer B output mode setting EVNB edge detection selection Not used $011 Timer B register (lower) $012 Timer B register (upper) $013 $014 Timer C clock source selection Reload on/off Timer C output mode selection Not used Not used $015 Timer C register (lower) $016 Timer C register (upper) $017 Timer D clock source selection $018 Reload on/off Not used Input capture selection EVND edge detection selection $019 Timer D register (lower) $01A $01B Timer D register (upper) $01C Not used $01F $020 Register flag area $023 $024 Serial transfer clock speed selection Not used Not used R22/SI/SO PMOS control SO idle H/L setting $025 Serial data register (lower) $026 $027 Serial data register (upper) Analog channel selection A/D conversion time $028 Not used $029 A/D data register (lower) $02A $02B A/D data register (upper) Realtime clock mode Power supply dividing On-chip power supply switch Display on/off $02C display selection resistor switch Input clock selection Duty selection $02D Clock output on/off Buzzer/clock selection Buzzer/clock source selection $02E Not used $02F PortD3DCR PortD2DCR PortD1DCR PortD0DCR $030 PortD7DCR PortD6DCR PorD5DCR PortD4DCR $031 $032 PortD10DCR PortD9DCR PortD8DCR PortD11DCR Not used $033 $034 PortR02DCR PortR01DCR PortR00DCR PortR03DCR $035 PortR12DCR PortR11DCR PortR10DCR PortR13DCR $036 PortR23DCR PortR22DCR PortR21DCR PortR20DCR $037 PortR32DCR PortR31DCR PortR30DCR PortR33DCR $038 PortR42DCR PortR41DCR PortR40DCR PortR43DCR $039 PortR53DCR PortR52DCR PortR51DCR PortR50DCR $03A PortR63DCR PortR62DCR PortR61DCR PortR60DCR PortR73DCR PortR72DCR PortR71DCR PortR70DCR $03B Not used $03C PortR80DCR PortR81DCR $03D Not used $03E Not used $03F Bank setting Not used
Figure 5 Special Function Register Area
31
HD404889/HD404899/HD404878/HD404868 Series
HD404899 Series
RAM address Bit 3 Bit 2 Bit 1 Bit 0
SSR MIS ESR PMR0 PMR1 PMR2 PMR3 PMR4 MSR1 MSR2 TMA TMB1 TMB2 TRBL/TWBL TRBU/TWBU TMC1 TMC2 TRCL/TWCL TRCU/TWCU TMD1 TMD2 TRDL/TWDL TRDU/TWDU
SMR1 SMR2 SRL SRU AMR ADRL ADRM ADRU LCR LMR BMR DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR5 DCR6 DCR7 DCR8
V
$000 Interrupt control bit area $003 System clock frequency 32 kHz oscillation stop setting 32 kHz frequency division System clock selection $004 division ratio switching ratio selection Interrupt frame period selection Not used $005 Pull-up MOS control Not used INT1 edge detection selection $006 Not used $007 Not used D1/INT1 D0/INT0 $008 $009 R03/WU3 R02/WU2 R01/WU1 R00/WU0 R13/TOB R12/BUZZ R11/EVND R10/EVNB $00A $00B R20/TOC R22/SI/SO R21/SCK R5/SEG9~12 R4/SEG5~8 R3/SEG1~4 $00C R6/SEG13~16 Not used Timer B lock on/off Timer D clock on/off Timer C clock on/off $00D Serial clock on/off A/D clock on/off Not used $00E $00F TimerA/Timer base Timer A clock source selection Reload on/off Timer B clock source selection $010 Timer B output mode setting EVNB edge detection selection Not used $011 Timer B register (lower) $012 Timer B register (upper) $013 $014 Timer C clock source selection Reload on/off Timer C output mode selection Not used Not used $015 Timer C register (lower) $016 Timer C register (upper) $017 Timer D clock source selection $018 Reload on/off Not used Input capture selection EVND edge detection selection $019 Timer D register (lower) $01A $01B Timer D register (upper) $01C Not used $01F $020 Register flag area $023 $024 Serial transfer clock speed selection Not used Not used R22/SI/SO PMOS control SO idle H/L setting $025 Serial data register (lower) $026 $027 Serial data register (upper) Analog channel selection A/D conversion time $028 A/D data register (lower) Not used $029 A/D data register (middle) $02A $02B A/D data register (upper) Realtime clock mode Power supply dividing On-chip power supply switch Display on/off $02C display selection resistor switch Input clock selection Duty selection $02D Clock output on/off Buzzer/clock selection Buzzer/clock source selection $02E Not used $02F PortD3DCR PortD2DCR PortD1DCR PortD0DCR $030 PortD7DCR PortD6DCR PorD5DCR PortD4DCR $031 $032 PortD10DCR PortD9DCR PortD8DCR PortD11DCR Not used $033 $034 PortR02DCR PortR01DCR PortR00DCR PortR03DCR $035 PortR12DCR PortR11DCR PortR10DCR PortR13DCR $036 PortR23DCR PortR22DCR PortR21DCR PortR20DCR $037 PortR32DCR PortR31DCR PortR30DCR PortR33DCR $038 PortR42DCR PortR41DCR PortR40DCR PortR43DCR $039 PortR53DCR PortR52DCR PortR51DCR PortR50DCR $03A PortR63DCR PortR62DCR PortR61DCR PortR60DCR PortR73DCR PortR72DCR PortR71DCR PortR70DCR $03B Not used $03C PortR80DCR PortR81DCR $03D Not used $03E Not used $03F Bank setting Not used
Figure 5 Special Function Register Area (cont)
32
HD404889/HD404899/HD404878/HD404868 Series
HD404878 Series
RAM address Bit 3 Bit 2 Bit 1 Bit 0
SSR MIS ESR PMR0 PMR1 PMR2 PMR3 PMR4 MSR1 MSR2 TMA TMB1 TMB2 TRBL/TWBL TRBU/TWBU TMC1 TMC2 TRCL/TWCL TRCU/TWCU TMD1 TMD2 TRDL/TWDL TRDU/TWDU
SMR1 SMR2 SRL SRU
LCR LMR BMR DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR5 DCR6 DCR7 DCR8
$000 Interrupt control bit area $003 System clock frequency 32 kHz oscillation stop setting 32 kHz frequency division System clock selection $004 division ratio switching ratio selection Interrupt frame period selection Not used $005 Pull-up MOS control Not used INT1 edge detection selection $006 Not used $007 Not used D1/INT1 D0/INT0 $008 $009 R03/WU3 R02/WU2 R01/WU1 R00/WU0 R13/TOB R12/BUZZ R11/EVND R10/EVNB $00A $00B R20/TOC R22/SI/SO R21/SCK R5/SEG9~12 R4/SEG5~8 R3/SEG1~4 $00C R6/SEG13~16 Not used Timer B lock on/off Timer D clock on/off Timer C clock on/off $00D Serial clock on/off Not used $00E $00F TimerA/Timer base Timer A clock source selection Reload on/off Timer B clock source selection $010 Timer B output mode setting EVNB edge detection selection Not used $011 Timer B register (lower) $012 Timer B register (upper) $013 $014 Timer C clock source selection Reload on/off Timer C output mode selection Not used Not used $015 Timer C register (lower) $016 Timer C register (upper) $017 Timer D clock source selection $018 Reload on/off Not used Input capture selection EVND edge detection selection $019 Timer D register (lower) $01A $01B Timer D register (upper) $01C Not used $01F $020 Register flag area $023 $024 Serial transfer clock speed selection Not used Not used R22/SI/SO PMOS control SO idle H/L setting $025 Serial data register (lower) $026 $027 Serial data register (upper) $028 $029 Not used $02A $02B Realtime clock mode Power supply dividing On-chip power supply switch Display on/off $02C display selection resistor switch Input clock selection Duty selection $02D Clock output on/off Buzzer/clock selection Buzzer/clock source selection $02E Not used $02F PortD3DCR PortD2DCR PortD1DCR PortD0DCR $030 PortD7DCR PortD6DCR PorD5DCR PortD4DCR $031 $032 PortD10DCR PortD9DCR PortD8DCR PortD11DCR Not used $033 $034 PortR02DCR PortR01DCR PortR00DCR PortR03DCR $035 PortR12DCR PortR11DCR PortR10DCR PortR13DCR $036 PortR23DCR PortR22DCR PortR21DCR PortR20DCR $037 PortR32DCR PortR31DCR PortR30DCR PortR33DCR $038 PortR42DCR PortR41DCR PortR40DCR PortR43DCR $039 PortR53DCR PortR52DCR PortR51DCR PortR50DCR $03A PortR63DCR PortR62DCR PortR61DCR PortR60DCR PortR73DCR PortR72DCR PortR71DCR PortR70DCR $03B Not used $03C PortR80DCR PortR81DCR $03D Not used $03E Not used $03F Not used
Figure 5 Special Function Register Area (cont)
33
HD404889/HD404899/HD404878/HD404868 Series
HD404868 Series
RAM address Bit 3 Bit 2 Bit 1 Bit 0
SSR MIS ESR PMR0 PMR1 PMR2 PMR3 PMR4 MSR1 MSR2 TMA TMB1 TMB2 TRBL/TWBL TRBU/TWBU TMC1 TMC2 TRCL/TWCL TRCU/TWCU
SMR1 SMR2 SRL SRU AMR ADRL ADRM ADRU LCR LMR BMR DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR5 DCR6 DCR7
$000 Interrupt control bit area $003 System clock frequency 32 kHz oscillation stop setting 32 kHz frequency division System clock selection $004 division ratio switching ratio selection Interrupt frame period selection Not used $005 Pull-up MOS control Not used INT1 edge detection selection $006 Not used $007 Not used D1/INT1 D0/INT0 $008 $009 Not used R02/WU2 R01/WU1 R00/WU0 R13/TOB R12/BUZZ Not used R10/EVNB $00A $00B R20/TOC R22/SI/SO R21/SCK R5/SEG9~12 R4/SEG5~8 R3/SEG1~4 $00C R6/SEG13~16 Not used Timer B lock on/off Timer C clock on/off $00D Serial clock on/off A/D clock on/off Not used $00E $00F TimerA/Timer base Timer A clock source selection Reload on/off Timer B clock source selection $010 EVNB edge detection selection Timer B output mode selection Not used $011 Timer B register (lower) $012 Timer B register (upper) $013 $014 Timer C clock source selection Reload on/off Timer C output mode selection Not used Not used $015 Timer C register (lower) $016 Timer C register (upper) $017 $018 Not used Not used $019 Not used $01A $01B Not used $01C Not used $01F $020 Register flag area $023 $024 Serial transfer clock speed selection Not used Not used R22/SI/SO PMOS control SO idle H/L setting $025 Serial data register (lower) $026 $027 Serial data register (upper) Analog channel selection A/D conversion time $028 A/D data register (lower) Not used $029 A/D data register (middle) $02A $02B A/D data register (upper) Realtime clock mode Power supply dividing On-chip power supply switch Display on/off $02C display selection resistor switch Input clock selection Duty selection $02D Clock output on/off Buzzer/clock selection Buzzer/clock source selection $02E Not used $02F PortD3DCR PortD2DCR PortD1DCR PortD0DCR $030 PortD7DCR PortD6DCR PorD5DCR PortD4DCR $031 $032 PortD8DCR Not used PortD9DCR Not used $033 $034 PortR01DCR PortR00DCR Not used PortR02DCR $035 PortR12DCR PortR11DCR PortR10DCR PortR13DCR $036 PortR23DCR PortR22DCR PortR21DCR PortR20DCR $037 PortR32DCR PortR31DCR PortR30DCR PortR33DCR $038 PortR42DCR PortR41DCR PortR40DCR PortR43DCR $039 PortR53DCR PortR52DCR PortR51DCR PortR50DCR $03A PortR63DCR PortR62DCR PortR61DCR PortR60DCR PortR73DCR PortR72DCR PortR71DCR PortR70DCR $03B Not used $03C $03D Not used $03E Not used $03F Not used
Figure 5 Special Function Register Area (cont)
34
HD404889/HD404899/HD404878/HD404868 Series
$040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04A $04B $04C $04D $04E $04F MR (0) MR (1) MR (2) MR (3) MR (4) MR (5) MR (6) MR (7) MR (8) MR (9) MR (10) MR (11) MR (12) MR (13) MR (14) MR (15) 960 Level Level Level Level Level Level Level Level Level Level Level Level Level Level Level 1,023 Level 16 $3C0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 $3FF
Bit 3 1020 1021 1022 1023 ST PC10 CA PC3
Bit 2 PC13 PC9 PC6 PC2
Bit 1 PC12 PC8 PC5 PC1
Bit 0 PC11 PC7 PC4 PC0 $3FC $3FD $3FE $3FF
(a) Memory registers
(b) Stack area PC13 to PC0 ST CA : Program counter : Status flag : Carry flag
Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position
Bank register (V: $03F) Bit Read/Write Initial value on reset Bit name 3 -- -- 2 -- -- 1 -- -- 0 R/W 0 V0
Not Used Not Used Not Used
V0 0 1
Bank area selection Bank 0 is selected Bank 1 is selected
Note: After reset, the value in the bank register is 0, and therefore bank 0 is selected. Applies to HD404889 and HD404899 Series.
Figure 7 Bank Register (V)
35
HD404889/HD404899/HD404878/HD404868 Series
Functional Description
Registers and Flags The MCU has nine registers and two flags for CPU operations. they are shown in figure 8 and described below.
3 Accumulator Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W (B) 1 W register Initial value: Undefined, R/W 3 X register Initial value: Undefined, R/W 3 Y register Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W 3 SPY register Initial value: Undefined, R/W (SPY) (SPX) (Y) (X) (W) (A)
0
0
0
0
0
0
0
Carry flag
Initial value: Undefined, R/W
0 (CA) 0 (ST) 0 (PC)
Status flag Program counter Initial value: $0000, no R/W Stack pointer Initial value: $3FF, no R/W
Initial value: 1, no R/W 13
9 1 1 1 1
5 (SP)
0
Figure 8 Registers and Flags Accumulator (A) and B register (B): The accumulator and B register are 4-bit registers used to hold the result of an ALU operation, and for data transfer to or from memory, an I/O area, or another register.
36
HD404889/HD404899/HD404878/HD404868 Series
W register (W), X register (X) and Y register (Y): The W register is a 2-bit register, and the X and Y registers are 4-bit registers, used for RAM register indirect addressing. The Y register is also used for D port addressing. SPX register (SPX) and SPY register (SPY): The SPX and SPY registers are 4-bit registers used as X register and Y register auxiliary registers, respectively. Carry flag (CA): This flag holds ALU overflow when an arithmetic/logic instruction is executed. It is also affected by the SEC, REC, ROTL, and ROTR instructions. The contents of the carry flag are saved to the stack when interrupt handling is performed, and are restored from the stack by the RTNI instruction (but are not affected by the RTN instruction). Status flag (ST): This flag holds ALU overflow when an arithmetic/logic or compare instruction is executed, and the result of an ALU non-zero or bit test instruction. It is used as the branch condition for the BR, BRL, CAL, and CALL instructions. The status flag is a latch-type flag, and does not change until the next arithmetic/logic, compare, or bit test instruction is executed. After a BR, BRL, CAL, or CALL instruction, the status flag is set to 1 regardless of whether the instruction is executed or skipped. The contents of the status flag are saved to the stack when interrupt handling is performed, and are restored from the stack by the RTNI instruction (but are not affected by the RTN instruction). Program counter (PC): This is a 14-bit binary counter that holds ROM address information. Stack pointer (SP): The stack pointer is a 10-bit register that holds the address of the next save space in the stack area. The stack pointer is initialized to $3FF by an MCU reset. The stack pointer is decremented by 4 each time data is saved, and incremented by 4 each time data is restored. The upper 4 bits of the stack pointer are fixed at 1111, so that a maximum of 16 stack levels can be used. There are two ways in which the stack pointer is initialized to $3FF: by an MCU reset as mentioned above, or by resetting the RSP bit with the REM or REMD instruction. Reset An MCU reset is performed by driving the RESET pin low. At power-on, and when subactive mode, watch mode, or stop mode is cleared, RESET should be input for at least tRC to provide the oscillation settling time for the oscillator.In other cases, the MCU is reset by inputting RESET for at least two instruction cycles. Table 1 shows the areas initialized by an MCU reset, and their initial values.
37
HD404889/HD404899/HD404878/HD404868 Series
Table 1 (1) Initial Values after MCU Reset
Item Program counter Status flag Stack pointer Interrupt Interrupt enable flag Abbr. (PC) (ST) (SP) (IE) (IF) (IM) (PDR) Initial value $0000 1 $3FF 0 0 1 Contents Program executed from ROM start address Branching by conditional branch instruction enabled Stack level is 0 All interrupts disabled No interrupt requests Interrupt requests masked
flags/ mask Interrupt request flag Interrupt mask I/O Port data register Data control registers Data control registers
All bits 1 "1" level output possible
(DCD0 to 2) All bits 0 Output buffer off (high impedance) (DCR0 to 7, All bits 0 DCR80, DCR81) (PMR0) (PMR1) (PMR2) (PMR3) (PMR4) (ESR) (TMA) (TMB1) (TMB2) (TMC1) (TMC2) (TMD1) (TMD2) (PSS) (PSW) (TCA) (TCB) (TCC) (TCD) (TWBU,L) (TWCU,L) (TWDU,L) --00 0000 0000 0000 0000 --00 0000 0000 -000 0000 -0-0000 -000 $000 $00 $00 $00 $00 $00 $X0 $X0 $X0 See port mode register 0 section See port mode register 1 section See port mode register 2 section See port mode register 3 section See port mode register 4 section See edge detection select register section See timer mode register A section See timer mode register B1 section See timer mode register B2 section See timer mode register C1 section See timer mode register C2 section See timer mode register D1 section See timer mode register D2 section
Port mode register 0 Port mode register 1 Port mode register 2 Port mode register 3 Port mode register 4 Edge detection select register Timers Timer mode register A Timer mode register B1 Timer mode register B2 Timer mode register C1 Timer mode register C2 Timer mode register D1 Timer mode register D2 Prescaler S Prescaler W Timer/counter A Timer/counter B Timer/counter C Timer/counter D Timer write register B Timer write register C Timer write register D
38
HD404889/HD404899/HD404878/HD404868 Series
Table 1 (1) (cont) Initial Values after MCU Reset
Item Serial interface Serial mode register 1 Serial mode register 2 Serial data register Octal counter A/D converter A/D mode register A/D data register (HD404889 Series) A/D data register (HD404899 Series) LCD LCD control register LCD mode register Bit registers Low speed on flag Watchdog timer on flag A/D start flag Direct transfer on flag Input capture status flag Input capture error flag Gear enable flag Others Miscellaneous register System clock select register (AMR) (ADRU,L) Abbr. (SMR1) (SMR2) (SRU,L) Initial value 0000 -0X$XX 000 0000 $7F See A/D mode register section See A/D data register section See A/D data register section See LCD control register section See LCD duty/clock control register section See low-power mode section See timer C section See A/D converter section See low-power mode section See timer D section See timer D section See system clock gear function See low-power mode and input/output sections See low-power mode and oscillator circuit sections See timer section See serial interface and A/D converter sections See Buzzer mode register section Contents See serial mode register 1 section See serial mode register 2 section
(ADRU,M,L) $1FF (LCR) (LMR) (LSON) (WDON) (ADSF) (DTON) (ICSF) (ICEF) (GEF) (MIS) (SSR) 0000 0000 0 0 0 0 0 0 0 0-00 0000 -000 --00 0000
Module standby register 1 (MSR1) Module standby register 2 (MSR2) Buzzer mode register (BMR)
Notes: 1. The state of registers and flags other than those listed above after an MCU reset is shown in table 1 (2). 2. X: Indicates invalid value, - indicates that the bit does not exist.
39
HD404889/HD404899/HD404878/HD404868 Series
Table 1 (2) Initial Values after MCU Reset
Item Carry flag Accumulator B register W register Abbr. (CA) (A) (B) (W) After Stop Mode Clearance by WU0 to WU3 Input Retain value immediately prior to entering stop mode After Other MCU Reset Value immediately prior to MCU reset is not guaranteed. Must be initialized by program.
X/SPX register (X/SPX) Y/SPY register (Y/SPY) RAM
Interrupts There are a total of nine interrupt sources, comprising wakeup input (WU 0 to WU 3), external interrupts (INT0, INT 1), timer/counter (timer A, timer B, timer C, timer D) interrupts, a serial interface interrupt, and an A/D converter interrupt. Each interrupt source is provided with an interrupt request flag, interrupt mask, and vector address, used for storing and controlling interrupt requests. In addition, an interrupt enable flag is provided to control interrupts as a whole. Of the interrupt sources, timers B and D share the same vector address, and the A/D converter and serial interface also share the same vector address. Software must therefore determine which of the interrupt sources is requesting an interrupt at the start of interrupt handling. Interrupt control bits and interrupt handling: The interrupt control bits are mapped onto RAM addresses $000 to $003 and $022 to $023, and can be accessed by RAM bit manipulation instructions. However, the interrupt request flags (IF) cannot be set by software. When the MCU is reset, the interrupt enable flag (IE) and interrupt request flags (IF) are initialized to 0, and the interrupt masks (IM) are initialized to 1. Figure 9 shows a block diagram of the interrupt control circuit, table 2 shows interrupt priorities and vector addresses, and table 3 lists the conditions for executing interrupt handling for each of the nine kinds of interrupt source. When the interrupt request flag is set to 1 and the interrupt mask is cleared to 0, an interrupt is requested. If the interrupt enable flag is set to 1 at this time, interrupt handling is started. The vector address corresponding to the interrupt source is generated by the priority control circuit. The interrupt handling sequence is shown in figure 10, and the interrupt handling flowchart in figure 11. When an interrupt is accepted, execution of the previous instruction is completed in the first cycle. In the second cycle, the interrupt enable flag (IE) is reset. In the second and third cycles, the contents of the carry flag, status flag, and program counter are saved on the stack. In the third cycle, a jump is made to the vector address and instruction execution is resumed from that address.
40
HD404889/HD404899/HD404878/HD404868 Series
In each vector address area, a JMPL instruction should be written that branches to the start address of the interrupt routine. In the interrupt routine, the interrupt request flag that caused interrupt handling must be reset by software. Table 2 Vector Addresses and Interrupt Priorities
Priority -- 1 2 3 4 5 6 7 Vector Address $0000 $0002 $0004 $0006 $0008 $000A $000C $000E
Interrupt Source RESET WU0 to WU3 INT0 INT1 Timer A Timer B, D Timer C Serial interface, A/D converter
41
HD404889/HD404899/HD404878/HD404868 Series
$000,0
I/E Interrupt request
$000,2
(WU0 to WU3 interrupt) IFWU
$000,3
IMWU Priority control circuit Vector address
$001,0
(INT0 interrupt) IF0
$001,1
IM0
$001,2
(INT1 interrupt) IF1
$001,3
IM1
$002,0
(Timer A interrupt) IFTA
$002,1
IMTA
$002,2
(Timer B interrupt) IFTB
$022,2
IFTD (Timer D interrupt)
$002,3
IMTB
$022,3
IMTD
$003,0
(Timer C interrupt) IFTC
$003,1
IMTC
$003,2
(A/D interrupt) IFAD
$023,2
IFS (Serial interrupt)
$003,3
IMAD
$023,3
IMS
Figure 9 Block Diagram of Interrupt Control Circuit
42
HD404889/HD404899/HD404878/HD404868 Series
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source Interrupt Control Bit IE IFWU*IMWU IF0*IM0 IF1*IM1 IFTA*IMTA WU0 to WU3 1 1 * * * INT0 1 0 1 * * * * * INT1 1 0 0 1 * * * * Timer A 1 0 0 0 1 * * * Timer B or Timer D Timer C 1 0 0 0 0 1 * * 1 0 0 0 0 0 1 * A/D or Serial 1 0 0 0 0 0 0 1
IFTB*IMTB+IFTD*IMTD * IFTC*IMTC IFAD*IMAD+IFS*IMS * *
Note: * Operation is not affected whether the value is 0 or 1.
Instruction cycle 1 2 3 4 5 6
Instruction execution*
Interrupt acceptance
Save to stack IE reset
Save to stack Vector address generated
Execution of JMPL instruction at vector address
Execution of instruction at start address of interrupt routine
Note: The stack is accessed and the IE reset after the instruction is executed, even if it is a 2cycle instruction.
Figure 10 Interrupt Sequence
43
HD404889/HD404899/HD404878/HD404868 Series
Power ON
RESET="0"? Yes
No
Interrupt request? No
Yes
IE="1"? Yes Accept interrupt
Execute instruction Reset MCU
PC(PC)+1
IE"0" Stack(PC) Stack(CA) Stack(ST)
PC$0002
Yes
WU0~WU3 interrupt? No
PC$0004
Yes
INT0 interrupt? No
PC$0006
Yes
INT1 interrupt? No
PC$0008
Yes
Timer A interrupt?
No PC$000A Yes Timer B, timer D interrupt? No PC$000C Yes Timer C interrupt?
No PC$000E (A/D, serial interrupt)
Figure 11 Interrupt Handling Flowchart
44
HD404889/HD404899/HD404878/HD404868 Series
Interrupt enable flag (IE: $000,0): The interrupt enable flag controls interrupt enabling/disabling of all interrupt requests as shown in table 4. The interrupt enable flag is reset by interrupt handling and set by the RTNI instruction. Table 4 Interrupt Enable Flag (IE: $000,0)
Interrupt Enabling/Disabling Interrupts disabled Interrupts enabled
Interrupt Enable Flag(IE) 0 1
Wakeup interrupt request flag (IFWU: $000,2): The wakeup interrupt request flag (IFWU) is set by the detection of a falling edge in WU0 to WU3 input in active mode, subactive mode,watch mode, or standby mode. In stop mode, when a falling edge is detected at the wakeup pin, the MCU waits for the oscillation settling time, then switches to active mode. The wakeup interrupt request flag (IFWU) is not set in this case. Wakeup interrupt mask (IMWU: $000,3): This bit masks an interrupt request by the wakeup interrupt request flag.
Edge detection select register (ESR: $006) Bit Read/Write Initial value on reset Bit name 3 -- -- -- 2 -- -- -- 1 W 0 ESR1 0 W 0 ESR0
ESR1 0 1
ESR0 0 1 0 1
INT1edge detect Not detected Falling edge detection Rising edge detection Both rising and falling edge detection
Figure 12 Edge Detection Select Register (ESR)
45
HD404889/HD404899/HD404878/HD404868 Series
External interrupt request flags (IF0, IF1: $001): IF0 is set by a falling edge in the INT0 input, and IF1 is set by a rising edge, falling edge, or both edges in the INT1 input (table 5). Interrupt edge selection is performed by means of the edge detection select register (ESR: $006) (figure 12). Table 5 External Interrupt Request Flags (IF0, IF1: $001)
Interrupt Request No external interrupt request External interrupt request generated
External Interrupt Request Flags (IF0, IF1) 0 1
External interrupt masks (IM0, IM1: $001): These bits mask interrupt requests by the external interrupt request flags (table 6). Table 6 External Interrupt Mask (IM: $001)
Interrupt Request External interrupt request enabled External interrupt request masked (held pending)
External Interrupt Masks (IM0, IM1) 0 1
Timer A interrupt request flag (IFTA: $002,0): The timer A interrupt request flag is set by timer A overflow output (table 7). Table 7 Timer A Interrupt Request Flag (IFTA: $002,0)
Interrupt Request No timer A interrupt request Timer A interrupt request generated
Timer A Interrupt Request Flag(IFTA) 0 1
Timer A interrupt mask (IMTA: $002,1): This bit masks an interrupt request by the timer A interrupt request flag (table 8). Table 8 Timer A Interrupt Mask (IMTA: $002,1)
Interrupt Request Timer A interrupt request enabled Timer A interrupt request masked (held pending)
Timer A Interrupt Mask (IMTA) 0 1
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HD404889/HD404899/HD404878/HD404868 Series
Timer B interrupt request flag (IFTB: $002,2): The timer B interrupt request flag is set by timer B overflow output (table 9). Table 9 Timer B Interrupt Request Flag (IFTB: $002,2)
Interrupt Request No timer B interrupt request Timer B interrupt request generated
Timer B Interrupt Request Flag (IFTB) 0 1
Timer B interrupt mask (IMTB: $002,3): This bit masks an interrupt request by the timer B interrupt request flag (table 10). Table 10 Timer B Interrupt Mask (IMTB: $002,3)
Interrupt Request Timer B interrupt request enabled Timer B interrupt request masked (held pending)
Timer B Interrupt Mask (IMTB) 0 1
Timer C interrupt request flag (IFTC: $003,0): The timer C interrupt request flag is set by timer C overflow output (table 11). Table 11 Timer C Interrupt Request Flag (IFTC: $003,0)
Interrupt Request No timer C interrupt request Timer C interrupt request generated (held pending)
Timer C Interrupt Request Flag (IFTC) 0 1
Timer C interrupt mask (IMTC: $003,1): This bit masks an interrupt request by the timer C interrupt request flag (table 12). Table 12 Timer C Interrupt Mask (IMTC: $003,1)
Interrupt Request Timer C interrupt request enabled Timer C interrupt request masked (held pending)
Timer C Interrupt Mask (IMTC) 0 1
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HD404889/HD404899/HD404878/HD404868 Series
Timer D interrupt request flag (IFTD: $022,2): (Applies to HD404889, HD404899, and HD404878 Series) The timer D interrupt request flag is set by timer D overflow output, or by an EVND input edge when used as an input capture timer (table 13). Table 13 Timer D Interrupt Request Flag (IFTD: $022,2)
Interrupt Request No timer D interrupt request Timer D interrupt request generated
Timer D Interrupt Request Flag (IFTD) 0 1
Timer D interrupt mask (IMTD: $022,3): (Applies to HD404889, HD404899, and HD404878 Series) This bit masks an interrupt request by the timer D interrupt request flag (table 14). Table 14 Timer D Interrupt Mask (IMTD: $022,3)
Interrupt Request Timer D interrupt request enabled Timer D interrupt request masked (held pending)
Timer D Interrupt Mask (IMTD) 0 1
Serial interrupt request flag (IFS: $023,2): The serial interrupt request flag is set on completion of serial data transfer, or if data transfer is halted midway (table 15). Table 15 Serial Interrupt Request Flag (IFS: $023,2)
Serial Interrupt Request Flag (IFS) Interrupt Request 0 1 No serial interrupt request Serial interrupt request generated
Serial interrupt mask (IMS: $023,3): This bit masks an interrupt request by the serial interrupt request flag (table 16). Table 16 Serial Interrupt Mask (IMS: $023,3)
Interrupt Request Serial interrupt request enabled Serial interrupt request masked (held pending)
Serial Interrupt Mask (IMS) 0 1
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HD404889/HD404899/HD404878/HD404868 Series
A/D interrupt request flag (IFAD: $003,2): (Applies to HD404889, HD404899, and HD404868 Series) The A/D interrupt request flag is set on completion of A/D conversion (table 17). Table 17 A/D Interrupt Request Flag (IFAD: $003,2)
A/D Interrupt Request Flag (IFAD) Interrupt Request 0 1 No A/D interrupt request A/D interrupt request generated
A/D interrupt mask (IMAD: $003,3): (Applies to HD404889, HD404899, and HD404868 Series) This bit masks an interrupt request by the A/D interrupt request flag (table 18). Table 18 A/D Interrupt Mask (IMAD: $003,3)
Interrupt Request A/D interrupt request enabled A/D interrupt request masked (held pending)
Serial Interrupt Mask (IMAD) 0 1
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HD404889/HD404899/HD404878/HD404868 Series
Operating Modes
The five operating modes shown in table 19 can be used for the MCU. The function of each mode is shown in table 20, and the state transition diagram among each mode in figure 13. Table 19 Operating Modes and Clock Status
Mode Name Active Activation method Standby Stop STOP instruction when TMA3 = 0 Watch STOP instruction when TMA3 = 1 Subactive*2 INT0/timer A or WU0 to WU3 interrupt request in watch mode
SBY RESET cancellation, instruction interrupt request, WU0 to WU3 input in stop mode STOP/SBY instruction in subactive mode (when direct transfer is selected) OP OP RESET input, STOP/SBY instruction OP OP RESET input, interrupt request
Status
System oscillator Subsystem oscillator
Stopped OP *
1
Stopped OP RESET input, INT0/timer A or WU0 to WU3 interrupt request
Stopped OP RESET input, STOP/SBY instruction
Cancellation method
RESET input, WU0 to WU3 input
Notes: OP: implies in operation. 1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (SSR: $004) 2. Subactive mode is an optional function; specify it on the fnction option list.
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HD404889/HD404899/HD404878/HD404868 Series
Table 20
Function CPU RAM Timer A Timer B Timer C Timer D *
4
Operation in Low-Power Dissipation Modes
Stop Mode Retained Retained Stopped Stopped Stopped Stopped Stopped * Stopped Stopped Retained
1
Watch mode Retained Retained OP Stopped Stopped Stopped Stopped * Stopped OP *
2 1
Standby Mode Retained Retained OP OP OP OP OP OP OP Retained
Subactive Mode*3 OP OP OP OP OP OP OP Stopped OP OP
Serial interface A/D * LCD I/O
5
Retained
Notes: OP: implies in operation. 1. Transmission/Reception is activated if a clock is input in external clock mode. However, interrupts stop. 2. When a 32 kHz clock source is used. 3. Subactive mode is an optional function specified on the function option list. 4. Applies to HD404889, HD404899, and HD404878 Series. 5. Applies to HD404889, HD404899, and HD404868 Series.
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HD404889/HD404899/HD404878/HD404868 Series
Reset by RESET pin input or watchdog timer Stop mode (TMA3=0,SSR3=0,LSON=0) fosc fx oCPU oCLK oPER : Stop : Active : Stop : Stop : Stop
Reset Active mode SBY instruction
WU0 to WU3
Standby mode fosc fx oCPU oCLK oPER : Active : Active : Stop : fcyc : fcyc
interrupt
fosc fx oCPU oCLK oPER
: Active : Active : fcyc : fcyc : fcyc (TMA3=0)
STOP (TMA3=0,SSR3=1,LSON=0) instruction fosc : Stop fx : Stop WU0 to WU3 oCPU : Stop oCLK : Stop STOP oPER : Stop instruction *4
fosc fx oCPU oCLK oPER
: Active : Active : Stop : fw : fcyc
SBY instruction
(TMA3=1) fosc fx oCPU oCLK oPER : Active : Active : fcyc : fw : fcyc
Subactive mode fosc fx oCPU oCLK oPER : Stop : Active : fSUB : fw : fSUB
*1
interrupt
STOP instruction *2 Timer A, WU0~WU3 or INT0 interrupt Watch mode fosc fx oCPU oCLK oPER : Stop : Active : Stop : fw : Stop fosc fx oCPU oCLK oPER : Stop : Active : Stop : fw : Stop STOP instruction *3 Timer A, WU0 to WU3 or INT0 interrupt
fosc : Main oscillator frequency fx : Sub-oscillator frequency (for realtime clock) fcyc : fOSC/32 or fOSC/4 (selected by software) fw : fx/8 fSUB : fx/8 or fx/4 (selected by software) oCPU : System clock oCLK : Clock for realtime clock oPER : Peripheral function clock LSON : Low speed on flag DTON : Direct transfer on flag TMA3 : Timer mode register A bit3
(TMA3=1,LSON=0)
(TMA3=1,LSON=1)
Transition Condition *1 *2 *3 *4 STOP/SBY instruction STOP/SBY instruction STOP/SBY instruction STOP/SBY instruction
DTON 1 0 Don't care 0
LSON 0 0 1 0
TMA3 1 1 1 0
Figure 13 MCU Status Transitions
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HD404889/HD404899/HD404878/HD404868 Series
Active mode: In active mode all functions operate. In this mode, the MCU operates on clocks generated by the OSC1 and OSC2 oscillator circuits. Standby mode: In standby mode the oscillators continue to operate but clocks relating to instruction execution halt. As a result, CPU operation stops, and registers, RAM, and the D port/R port set for output retain their state immediately prior to entering standby mode. Interrupts, timers, the serial interface, and other peripheral functions continue to operate. Power consumption is lower than in active mode due to the halting of the CPU. The MCU is switched to standby mode by executing the SBY instruction in active mode. Standby mode is cleared by RESET input or an interrupt request. When standby mode is cleared by RESET input, an MCU reset is performed. When standby mode is cleared by an interrupt request, the MCU enters active mode and executes a instruction following the SBY instruction. After executing the instruction, if the interrupt enable flag is set to 1, interrupt handling is executed; if the interrupt enable flag is cleared to 0, the interrupt request is held pending and normal instruction execution is continued. MCU operation flowchart is shown in figure 14.
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HD404889/HD404899/HD404878/HD404868 Series
Stop mode Standby mode Watch mode
RESET=0? No RESET=0? Yes WU0 to WU3 = ? Yes Yes
No
IFWU*IMWU =1? Yes
No
No
IF0*IM0 = 1? Yes
No
IF1*IM1 = 1? Yes*
No
IFTA * IMTA = 1? Yes System clock oscillator started
No
IFTB * IMTB+ IFTD*IMTD = 1?
No
Yes* System reset IFTC* IMTC = 1? Yes* IFAD*IMAD+ IFS*IMS = 1? Yes* No No
System clock oscillator started
NOP
Next Instruction execution
System clock oscillator started
No
IF = 1, IM = 0, IE = 1? Yes
Note: Only when clearing from standby mode
Next Instruction execution
Interrupts enabled
Figure 14 MCU Operation Flowchart
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HD404889/HD404899/HD404878/HD404868 Series
Stop mode: In stop mode, all MCU function stop except that states prior to entry into stop mode are retained. This mode thus has the lowest power consumption of all operating mode. In stop mode, the OSC1 and OSC2 oscillators stop. Bit 3 (SSR3) of the system clock select register (SSR: $004) (figure 24) can be used to select the active (= 0) or stopped (= 1) state for the X1 and X2 oscillators. The MCU is switched to stop mode by executing a STOP instruction while bit 3 (TMA3) of timer mode register A (TMA: $00F) is cleared to 0 in active mode. Stop mode is cleared by RESET or WU0 to WU 3 input. When stop mode is cleared by RESET, the RESET signal should be input for at least the oscillation settling time (tRC) (see "AC Characteristics") shown in figure 15. Then, the MCU is initialized and starts instruction execution from the start (address 0) of the program. When the MCU detects a falling edge at WU0 to WU3 in stop mode, it automatically waits for the oscillation settling time, then switches to active mode. After the transition to active mode, the MCU resumes program execution from the instruction following the STOP instruction. If stop mode is cleared by wakeup input, RAM data and registers retain their values prior to entering stop mode.
Stop mode Oscillator
Internal clock
RESET
tres STOP instruction executed (At least oscillation settling time (tRC))
Figure 15 Timing Chart for Clearing Stop Mode by RESET Input Note: If stop mode is cleared by wakeup input when an external clock is used as the system clock (OSC1), the subclock should not be stopped in stop mode. Watch mode: In watch mode, the realtime clock function (timer A) and LCD function using the X1 and X2 oscillators operate, but other functions stop. This mode thus has the second lowest power consumption after stop mode, and is useful for performing realtime clock display only. In watch mode, the OSC 1 and OSC2 oscillators stop but the X1 and X2 oscillators continue to operate. The MCU is switched to watch mode by executing a STOP instruction while TMA3 = 1 in active mode, or by executing a STOP/SBY instruction in subactive mode.
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HD404889/HD404899/HD404878/HD404868 Series
Watch mode is cleared by RESET input or an INT0,timer A or WU0 to WU3 interrupt request. For RESET input, refer to the section on stop mode. When watch mode is cleared by an INT0,timer A or WU0 to WU3 interrupt request, the mode transition depends on the value of the LSON bit: the MCU enters active mode if LSON = 0, and enters subactive mode if LSON = 1. In the case of a transition to active mode, interrupt request generation is delayed to secure the oscillation settling time: the delay is the tRC set time for the timer A interrupt, and, for the INT0 interrupt or WU0 to WU3 interrupt, Tx (T + tRC < Tx < 2T + tRC) if bit 1 and 0 (MIS1, MIS0) of the miscellaneous register are set to 00, or Tx (tRC < Tx < T + tRC) if MIS1 and MIS0 are set to 01 or 10 (figures 16 and 17). Other operations when the transition is made are the same as when watch mode is cleared (figure 14). Subactive mode: In subactive mode, the OSC1 and OSC2 oscillator circuits stop and the MCU operates on clocks generated by the X1 and X2 oscillator circuits. In this mode, functions other than the A/D converter operate, but since the operating clocks are slow, power consumption is the lowest after watch mode. A CPU instruction processing speed of 244 s or 122 s can be selected according to whether bit 2 (SSR2) of the system clock select register (SSR: $004) is set to 1 or cleared to 0. The value of the SSR2 bit should be changed (01 or 10) only in active mode. If the value is changed in subactive mode, the MCU may operate incorrectly. Subactive mode is cleared by executing a STOP/SBY instruction. A transition is then made to either watch mode or active mode according to the value of the low speed on flag (LSON: $020,0) and the direct transfer on flag (DTON: $020,3). Subactive mode is a function option, and should be specified in the function option list. Interrupt frame: In watch mode and subactive mode, oCLK is supplied to the timer A, WU0 to WU3, and INT0 acceptance circuits. Prescaler W and timer A operate as time bases, and generate interrupt frame timing. Either of two values can be selected for the interrupt frame period, T, by means of the miscellaneous register (MIS: $005) (figure 17). In watch mode and subactive mode, the timing for generation of timer A,INT0 and WU0 to WU3 interrupts is synchronized with the interrupt frame. Except for the case of an active mode transition, the interrupt strobe timing is used for interrupt request generation. Timer A generates overflow and interrupt requests at the interrupt strobe timing.
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HD404889/HD404899/HD404878/HD404868 Series
Oscillation stabilization period Active mode Watch mode Active mode
Interrupt strobe INT0 Interrupt request generation T Only in case of transition to active mode T TX T: Interrupt frame period tRC : Oscillation stabilization period tRC
Note: If the time from the fall of the INT0 or WU0 to WU3 signal until the interrupt is accepted and active mode is entered and is designated TX, then TX will be in the following range : T+tRCTX2T+tRC (MIS1, MIS0=00) tRCTXT+tRC (MIS1, MIS0=01 or 10)
Figure 16 Interrupt Frame
Miscellaneous Register (MIS: $005) Bit Read/Write Reset Bit name 3 W 0 MIS3 2 1 W 0 MIS1 0 W 0 MIS0
Buffer control See section 3, Input/Output, and Figure 33
MIS1 0 1 Notes:
MIS0 0 1 0 1
Interrupt Frame Oscillation Settling Oscillator Circuit period T(ms)*1 Time tRC(ms)*1 Condition 0.24414 3.90625 3.90625 0.12207(0.24414)*2 External clock input 7.8125 Ceramic resonator 31.25 Crystal resonator Not used
1. T and tRC values are for use of a 32.768 kHz crystal oscillator at the X1-X2 pins. 2. This value applies only in case of direct transition operation.
Figure 17 Miscellaneous Register (MIS)
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HD404889/HD404899/HD404878/HD404868 Series
Direct transition from subactive to active mode: A direct transition can be made from subactive mode to active mode by controlling the direct transfer on flag (DTON: $020,3) and low speed on flag (LSON: $020,0). The procedure is shown below. (a) Set LSON = 0 and DTON = 1 in subactive mode. (b) Execute a STOP or SBY instruction. (c) After the lapse of the MCU internal processing time and the oscillation settling time, the MCU automatically switches from subactive mode to active mode (figure 18). Notes: 1. The DTON flag ($020,3) can be set in only subactive mode. It is always in the reset state in active mode. 2. The condition for transition time TD from the subactive mode to active mode is as follows: tRC < TD < T + tRC.
STOP/SBY instruction execution Subactive mode (Set LSON =0, DTON =1) MCU internal processing time Oscillation stabilization time Active mode
Interrupt strobe
Direct transition completion timing T TD tRC T: Interrupt frame period tRC: Oscillation settling time TD: Direct transition time
Figure 18 Direct Transition Timing MCU operation sequence: The MCU operates in accordance with the flowchart shown in figure 19. RESET input is asynchronous input, and the MCU immediately enters the reset state upon RESET input, regardless of its current state. In the low-power mode operation sequence, if a STOP/SBY instruction is executed while the IE flag is cleared and the interrupt flag is set, releasing the relevant interrupt mask, the STOP/SBY instruction is canceled (regarded as NOP) and the next instruction is executed. Therefore, when executing a STOP/SBY instruction, all interrupt flags must be cleared, or interrupts masked, beforehand.
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HD404889/HD404899/HD404878/HD404868 Series
STOP/SBY instruction
IF=1 IM=0 Yes
No
Standby/watch mode
Stop Mode
No
IE=0 Yes No
Interrupt handling routine
IF=1 IM=0 Yes
No
WU0~WU3 = Yes
Clearing Standby watch mode Hardware NOP Execution Hardware NOP Execution
Clearing Stop mode
NOP
PC(PC)+1 PC(PC)+1 PC(PC)+2
Instruction Execution
Instruction Execution
MCU Operation Cycle
Note: See figure 14, MCU Operation Flowchart, for IF and IM operation.
Figure 19 MCU Operating Sequence (Low-Power Mode Operation)
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HD404889/HD404899/HD404878/HD404868 Series
Usage notes: In watch mode and subactive mode, an interrupt will not be detected correctly if the INT0 or WU0 to WU3 high or low-level period is shorter than the interrupt frame period. The MCU's edge sensing method is shown in figure 20. The MCU samples the INT0 and WU0 to WU3 signals at regular intervals, and if consecutive sampled values change from high to low, it determines that a falling edge has been generated. Interrupt detection errors occur since this sampling is performed at the interrupt frame period. If the highlevel period of the INT0 or WU0 to WU3 signal is within an interrupt frame, as shown in figure 21 (a), the signal will be low at point A and point B, with the result that the falling edge will not be recognized. Similarly, If the low-level period of the INT0 or WU0 to WU3 signal is within an interrupt frame, as shown in figure 21 (b), the signal will be high at point A and point B, with the result that the falling edge will not be recognized. In watch mode and subactive mode, therefore, ensure that the high-level and low-level periods of the INT0 and WU 0 to WU 3 signals is at least as long as the interrupt frame period.
INT0 or WU0 to WU3 Sampling High Low Low
Figure 20 Edge Sensing Method
(a) High-level mode (b) Low-level mode
INT0 or WU0 to WU3
INT0 or WU0 to WU3
Interrupt frame
Point A: Low
Point B: Low
Interrupt frame
Point A: High
Point B: High
Figure 21 Sampling Examples
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HD404889/HD404899/HD404878/HD404868 Series
Internal Oscillator Circuit
Figure 22 shows the clock pulse generator circuit. As shown in table 21, a ceramic oscillator or crystal oscillator can be connected to OSC1 and OSC2, and a 32.768 kHz crystal oscillator can be connected to X1 and X2. External clock operation is possible for the system oscillator. Set bit 1 (SSR1) of the system clock select register (SSR: $004) according to the frequency of the oscillator connected to OSC1 and OSC2 (figure 24). Note: If the setting of bit 1 in the system clock select register does not match the frequency of the system oscillator, the subsystem using 32.768 kHz oscillation will not operate correctly.
LSON OSC2 System oscillator fOSC 1/4 or 1/32 fcyc Timing tcyc generation division circuit* circuit System clock selection circuit
oCPU
CPU *ROM *RAM * Registers, flags *I/O
OSC1
oPER
X2 Sub system clock oscillator X1 Time base clock selection circuit fx 1/8 or 1/4 fSUB Timing division tsubcyc generator circuit* circuit
Peripheral functions Interrupts
TMA3 bit
oCLK
1/8 division circuit
Timing fW twcyc generation circuit
Timer A interrupts
Notes: The division ratio can be selected by setting bit 0 or bit 2 in the system clock select register (SSR:$004).
Figure 22 Clock Pulse Generator Circuit
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HD404889/HD404899/HD404878/HD404868 Series
System Clock Gear Function
The MCU has a built-in system clock gear function that allows the system clock divided by 4 or by 32 to be selected by software for the instruction execution time. Efficient power consumption can be achieved by operating at the divided-by-4 rate when high-speed processing is needed, and at the divided-by-32 rate at the other times. Figure 23 shows the system clock conversion method. System clock conversion from division-by-4 to division-by-32 is performed as follows. First, make the division-by-32 setting (SSR0 write), then set the gear enable flag (GEF: $021,3). This flag is used to distinguish between gear conversion and a transition to standby mode. Next, execute an SBY instruction. When the gear enable flag is not set, standby mode is entered; when this flag is set, gear conversion mode is entered. In this case a transition is made to standby mode for the duration of the gear conversion, but after the synchronization time has elapsed, a transition is made automatically to active mode. As soon as the transition is made to active mode, the gear enable flag is reset. The same procedure is used for conversion from division-by-32 to division-by-4. Clear all interrupts, then disable interrupts, before carrying out gear conversion. Incorrect operation may result if an interrupt is generated during gear conversion.
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HD404889/HD404899/HD404878/HD404868 Series
Division-by-32 setting (SSR0 = 1)
Set gear enable flag Execute SBY instruction Synchronization time Execute next instruction
Division-by-4 setting (SSR0 = 0) Set gear enable flag Execute SBY instruction Synchronization time Execute next instruction
Figure 23 System Clock Division Ratio Conversion Flowchart
63
HD404889/HD404899/HD404878/HD404868 Series
System clock select register (SSR: $004) Bit Read/Write Initial value on reset Bit name 3 W 0 SSR3* 2 W 0 SSR2 1 W 0 SSR1 0 W 0 SSR0
System clock division ratio switch 0 1 Division-by-4 (fcyc - fOSC/4) Division-by-32 (fcyc - fOSC/32)
System clock division ratio switch 0 1 fosc=0.4-1.0MHz fosc=1.6-4.5MHz
Subsystem clock division ratio switch 0 1 Subsystem clock stop setting 0 1 Subsystem clock operates in stop mode Subsystem clock stops in stop mode fSUB=fx/8 fSUB=fx/4
Note: * If the subsystem clock is not used, this bit must be set to 1 following power-on and reset. If it is set to 0 (the initial value), malfunctioning may occur in the stop mode.
Figure 24 System Clock Select Register
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HD404889/HD404899/HD404878/HD404868 Series
Table 21 Oscillator Circuit Examples
Circuit Structure External clock operation
External oscillator Open
Circuit Constants
OSC1
OSC2
Ceramic oscillator (OSC1, OSC 2)
C1 OSC1
Ceramic oscillator
Ceramic oscillator: CSA4.00MG (Murata)
Rf GND C2
OSC2
Rf=1M20% C1=C2=30pF20%
Crystal oscillator (OSC1, OSC 2)
C1 OSC1 Crystal oscillator Rf GND C2 OSC2
Rf=1M20% C1=C2=10-22pF20%
Crystal: Equivalent circuit at left C0=7pFmax. RS=100max.
OSC1
L
CS C0
RS
OSC2
Crystal oscillator (X1, X2)
C1 X1 Crystal oscillator X2 GND C2 L X1 C0 CS RS X2
Crystal: 32.768 kHz: MX38T (Nihon Denpa Kogyo) C1=C2=20pF20% RS=14k C0=1.5pF
Notes: 1. With a crystal or ceramic oscillator, circuit constants will differ depending on the resonator, stray capacitance in the interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the resonator manufacturer. 2. Make the connections between the OSC1 and OSC 2 pins (X1 and X2 pins) and external components as short as possible, and ensure that no other lines cross these lines (see layout example in figure 25). 3. When 32.768 kHz crystal oscillation is not used, fix the X1 pin at V CC and leave the X2 pin open.
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HD404889/HD404899/HD404878/HD404868 Series
RESET
X1
X2
GND
OSC2
OSC1
TEST GND
Figure 25 Typical Layouts of Crystal and Ceramic Oscillator
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HD404889/HD404899/HD404878/HD404868 Series
Input/Output
The MCU has 46 input/output pins (D 0 to D11, R0 to R7, R80, and R81) in the HD404889, HD404899, and HD404878 Series, or 41 input/output pins (D 0 to D9, R00, R01, R02, and R1 to R7) in the HD404868 Series. The features of these pins are described below. * The four pins D 0 to D3 are source large-current (10 mA max.) I/O pins. * The eight pins D4 to D11 are sink large-current (15 mA max.) I/O pins. * I/O pins comprise pins (D0, D1, R0, R 1, R2 0 to R22, R3 to R7, R80, and R8 1) that also have a peripheral function (timer, serial interface, etc.). With these pins, the peripheral function setting has priority over the D port or R port pin setting. When a peripheral function setting has been made for a pin, the pin function and input/output mode will be switched automatically in accordance with that setting. * Selection of input or output for I/O pins, or selection of the port or peripheral function for pins multiplexed as peripheral function pins, is performed by the program. * All output of the peripheral function pins are CMOS outputs. The SO pin and R2 2 port pin can be designated as NMOS open-drain output by the program. * A reset clears peripheral function selection. And since the data control registers (DCD, DCR) are also reset, input/output pins go to the high-impedance state. * Each I/O pin has a built-in pull-up MOS that can be turned on and off individually by the program. Figure 26 shows the I/O buffer configuration, and table 22 shows I/O pin circuit configuration control by the program. Table 23 shows the circuit configuration of each I/O pin.
VCC Pull-up control signal pull-up MOS VCC PMOS Buffer control signal DCD, DCR MIS3
Output data NMOS Input data Input control signal
PDR
Figure 26 I/O Pin Circuit Configuration
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HD404889/HD404899/HD404878/HD404868 Series
Table 22 Programmable I/O Circuits
0 0 0 PMOS NMOS pull-up MOS Note: -- : OFF -- -- -- 1 -- -- -- 0 -- ON -- 1 1 ON -- -- 0 -- -- -- 0 1 -- -- ON 0 -- ON -- 1 1 1 ON -- ON
MIS3 (bit 3 of MIS) DCD,DCR PDR CMOS buffer
Table 23 Circuit Configurations of I/O Pins
Type I/O pins Circuit Configuration VCC VCC Pull-up control signal Buffer control signal Output data PDR Input data Input control signal VCC VCC Pull-up control signal Buffer control signal Output data MIS3 DCR SMR22 PDR MIS3 DCD, DCR Pins D0-D11 R0 0-R03 R1 0-R13 R2 0, R2 1, R2 3 R3 0-R33 R4 0-R43 R5 0-R53 R6 0-R63 R7 0-R73 R8 0-R81 R2 2
Input data Input control signal Perip- I/O pins heral function pins VCC VCC Pull-up control signal MIS3 PDR I/O control signal SCK SCK
Output data
Input data
SCK
Note: In a reset, since the I/O control registers are reset, input/output pins go to the high-impedance state and peripheral function selections are cleared.
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HD404889/HD404899/HD404878/HD404868 Series
Table 23
Type Peripheral function pins Output pins
Circuit Configurations of I/O Pins (cont)
Circuit Configuration VCC VCC Pull-up control signal PMOS control signal Output data MIS3 PDR SMR22 SO Pins SO
VCC
VCC
Pull-up control signal
MIS3 PDR TOB, TOC, BUZZ
TOB, TOC, BUZZ
Output data
Input pins VCC
Input data
RESET
RESET
MIS3 PDR
WU0-WU3, INT0, INT1, EVNB, EVND, SI
WU0-WU3 etc.
VCC MIS3 PDR
AN 0-AN5*
A/D input Input control signal
Notes: In a reset, since the I/O control registers are reset, input/output pins go to the high-impedance state and peripheral function selections are cleared. * Applies to HD404889, HD404899, and HD404868 Series.
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HD404889/HD404899/HD404878/HD404868 Series
D Port The D port consists of 12 I/O pins (10 I/O pins in the HD404868 Series) that are addressed bit-by-bit. Ports D0 to D3 are source large-current I/O pins, and ports D4 to D11 (ports D 4 to D9 in the HD404868 Series) are sink large-current I/O pins. The D port can be set and reset by the SED and RED instructions or the SEDD and REDD instructions. Output data is stored in the port data register (PDR) for each pin. The entire D port can be tested by the TD or TDD instruction. The D port output buffer is turned on and off by the D port data control registers (DCD0 to DCD2: $030 to $032). The DCD registers are mapped onto memory addresses (figure 27). Ports D0 and D1 are multiplexed as interrupt input pins INT0 and INT1, respectively. Setting as interrupt pins is performed by bits 0 and 1 (PMR00, PMR01) of port mode register 0 (PMR0: $008) (figure 28).
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HD404889/HD404899/HD404878/HD404868 Series
Data control registers (DCD0-2 : $030-$032) (DCR0-8 : $034-$03C) Register Name Bit Read/Write DCD0-DCD2 Reset Bit name Read/Write DCR0-DCR8 Reset Bit name 3 W 0 DCD03-DCD23 W 0 DCR03-DCR73 All bits 0 1 2 W 0 DCD02-DCD22 W 0 DCR02-DCR72 1 W 0 DCD01-DCD21 W 0 DCR01-DCR81 0 W 0 DCD00-DCD20 W 0 DCR00-DCR80
CMOS buffer control CMOS buffer off (high impedance) CMOS buffer active
Correspondence between each bit of DCD and DCR and ports Register Name DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR5 DCR6 DCR7 DCR8 Bit 3 D3 D7 D11* R03* R13 R23 R33 R43 R53 R63 R73 Bit 2 D2 D6 D10* R02 R12 R22 R32 R42 R52 R62 R72 Bit 1 D1 D5 D9 R01 R11 R21 R31 R41 R51 R61 R71 R81* Bit 0 D0 D4 D8 R00 R10 R20 R30 R40 R50 R60 R70 R80*
Note: * Applies to HD404889, HD404899, and HD404878 Series
Figure 27 Data Control Registers (DCD, DCR)
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HD404889/HD404899/HD404878/HD404868 Series
R Port The R port consists of 34 I/O pins (31 I/O pins in the HD404868 Series) that are addressed in 4-bit units. Input can be performed by means of the LAR and LBR instructions, and output by means of the LRA and LRB instructions. Output data is stored in the port data register (PDR) for each pin. The R port output buffer is turned on and off by the R port data control registers (DCR0 to DCR8: $034 to $03C). The DCR registers are mapped onto memory addresses (figure 27). Ports R0 0 to R03 are multiplexed as wakeup input pins WU0 to WU3, respectively. Setting of these pins as peripheral function pins is performed by port mode register 1 (PMR1: $009) (figure 29). Ports R10 and R1 1 are multiplexed as peripheral function pins EVNB and EVND, respectively. Setting of these pins as peripheral function pins is performed by bits 0 and 1 (PMR20, PMR21) of port mode register 2 (PMR2: $00A) (figure 30). Ports R12 to R13 and R20 are multiplexed as peripheral function pins BUZZ, TOB, and TOC, respectively. Setting of these pins as peripheral function pins is performed by bits 2 and 3 (PMR22, PMR23) of port mode register 2 (PMR2: $00A) and bit 0 (PMR30) of port mode register 3 (PMR3: $00B)(figures 30 and 31). Ports R21 and R22 are multiplexed as peripheral function pins SCK and SI/SO, respectively. Setting of these pins as peripheral function pins is performed by bits 1 to 3 (PMR31 to PMR33) of port mode register 3 (PMR3: $00B) (figure 31). Ports R3 to R6 are multiplexed as peripheral function pins SEG1 to SEG16, respectively. Setting of these pins as segment pins is performed every 4 pins in 4-bit units by port mode register 4 (PMR4: $00C) (figure 32). Ports R70 to R73 and R80 to R81 also function as peripheral function pins AN 0 to AN5 (HD404889, HD404899, and HD404868 series only). Peripheral function pin setting of these pins is performed using bits 1 to 3 (AMR1 to AMR3) of the A/D mode register (AMR :$028). (See Figure 74 in A/D Converter.)
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HD404889/HD404899/HD404878/HD404868 Series
Port mode register 0 (PMR0: $008) Bit Read/Write Initial value on reset Bit name Not used Not used 3 2 1 W 0 PMR01 0 W 0 PMR00
PMR00 0 1 PMR01 0 1
D0/INT0 pin mode selection D0 INT0
D1/INT1 pin mode selection D1 INT1
Figure 28 Port Mode Register 0 (PMR0: $008)
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HD404889/HD404899/HD404878/HD404868 Series
Port mode register 1 (PMR1: $009) Bit Read/Write Initial value on reset Bit name 3 W 0 PMR13* 2 W 0 PMR12 1 W 0 PMR11 0 W 0 PMR10
PMR10 0 1 PMR11 0 1 PMR12 0 1 PMR13 0 1
R00/WU0 pin mode selection R00 WU0
R01/WU1 pin mode selection R01 WU1
R02/WU2 pin mode selection R02 WU2
R03/WU3 pin mode selection R03 WU3
Note: * Applies to HD404889, HD404899, and HD404878 Series
Figure 29 Port Mode Register 1 (PMR1: $009)
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HD404889/HD404899/HD404878/HD404868 Series
Port mode register 2 (PMR2: $00A) Bit Read/Write Initial value on reset Bit name 3 W 0 PMR23 2 W 0 PMR22 1 W 0 PMR21* 0 W 0 PMR20
PMR20 0 1 PMR21 0 1 PMR22 0 1 PMR23 0 1
R10/EVNB pin mode selection R10 EVNB
R11/EVND pin mode selection R11 EVND
R12/BUZZ pin mode selection R12 BUZZ
R13/TOB pin mode selection R13 TOB
Note: * Applies to HD404889, HD404899, and HD404878 Series
Figure 30 Port Mode Register 2 (PMR2: $00A)
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HD404889/HD404899/HD404878/HD404868 Series
Port mode register 3 (PMR3: $00B) Bit Read/Write Initial value on reset Bit name 3 W 0 PMR33 2 W 0 PMR32 1 W 0 PMR31 0 W 0 PMR30
PMR30 0 1 PMR31 0 1 PMR33 0 1 PMR32 0 1 : Don't care
R20/TOC pin mode selection R20 TOC
R21/SCK pin mode selection R21 SCK
R22/SI/SO pin mode selection R22 SI SO
Figure 31 Port Mode Register 3 (PMR3: $00B)
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HD404889/HD404899/HD404878/HD404868 Series
Port mode register 4 (PMR4: $00C) Bit Read/Write Initial value on reset Bit name 3 W 0 PMR43 2 W 0 PMR42 1 W 0 PMR41 0 W 0 PMR40
PMR40 R3/SEG1 to SEG4 pin mode selection 0 1* PMR41 0 1* PMR42 0 1* PMR43 0 1* R3 SEG1-4
R4/SEG5 to SEG8 pin mode selection R4 SEG5-8
R5/SEG9 to SEG12 pin mode selection R5 SEG9-12
R6/SEG13 to SEG16 pin mode selection R6 SEG13-16
* : When use as a segment output pin, write its port data register (PDR) to '0'
Figure 32 Port Mode Register 4 (PMR4: $00C) Pull-Up MOS Control Program-controllable pull-ups MOS are incorporated in all I/O pins. On/off control of all pull-ups MOS is performed by bit 3 (MIS3) of the miscellaneous register (MIS: $005) and the port data register (PDR) for each pin, enabling the pull-up MOS to be turned on or off independently for each pin (table 22, figure 33). Except for analog input multiplexed pins, the pull-up MOS on/off setting can be made independent of the setting as an on-chip supporting module pin.
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HD404889/HD404899/HD404878/HD404868 Series
Miscellaneous register (MIS: $005) Bit Read/Write Initial value on reset Bit name 3 W 0 MIS3 2 -- -- -- 1 W 0 MIS1 0 W 0 MIS0
tRC selection (See figure 17 in the Operating Modes section) MIS3 0 1 pull-up MOS control All pull-ups MOS off pull-up MOS active
Figure 33 Miscellaneous Register (MIS:$005) Handling of I/O Pins Not Used by User System If I/O pins that are not used by the user system are left floating, they may generate noise that can result in chip malfunctions. Therefore, the pin potential must be fixed. In this case, pull the pins up to VCC with the built-in pull-up MOS or with an external resistor of approximately 100 k.
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HD404889/HD404899/HD404878/HD404868 Series
Prescalers
The MCU has the following two prescalers, S and W. The operating conditions for each prescaler are shown in table 24, and the output supply destinations in figure 34. Timer A to D input clocks other than external events, serial transfer clocks other than external clocks, and the LCD circuit operating clock are selected from the prescaler outputs in accordance with the respective mode register. Prescaler Operation Prescaler S (PSS): Prescaler S is an 11-bit counter that has the system clock as input. When the MCU is reset, prescaler S is reset to $000, then divides the system clock. Prescaler S operation is stopped by a reset by the MCU, and in stop mode and watch mode. It does not stop in any other modes. Prescaler W (PSW): Prescaler W is a counter that has a clock divided from the X1 input (32 kHz crystal oscillation) as input. When the MCU is reset, prescaler W is reset to $00, then divides the input clock. Prescaler W can also be reset by software. Table 24
Prescaler Prescaler S
Prescaler Operating Conditions
Input Clock Reset Conditions Stop Conditions MCU reset, Stop mode, Watch mode MCU reset, Stop mode
System clock in active and MCU reset, Stop mode standby modes, Subsystem clearance clock in subactive mode Clock obtained by division- MCU reset, Software* by-8 of 32.768 kHz oscillation by subsystem clock oscillator
Prescaler W
Note: If bits TMA3 to TMA1 in timer mode register A (TMA) are all set to 1, PSW is cleared to $00.
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HD404889/HD404899/HD404878/HD404868 Series
Subsystem clock
Prescaler W
LCD controller driver circuit Timer A Timer B Timer C Timer D
System clock
Clock selector
Prescaler S
Serial interface
Figure 34 Prescaler Output Destinations
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HD404889/HD404899/HD404878/HD404868 Series
Timers
The MCU incorporates four timers, A to D, in the HD404889, HD404899, and HD404878 Series, or three timers, A to C, in the HD404868 Series. * * * * Timer A: Free-running timer Timer B: Multifunctional timer Timer C: Multifunctional timer Timer D: Multifunctional timer
Timer A is an 8-bit free-running timer. Timers B, C, and D are 8-bit multifunctional timers; Each one of their have the functions shown in table 25 and their operating mode can be set by the program. Table 25
Functios Clock source Prescaler S Prescaler W External event Timer functions Free-running Time-base Event counter Reload Watchdog Input Capture Timer outputs Toggle PWM Note: -- implies not available
Timer Functions
Timer A Available Available -- Available Available -- -- -- -- -- -- Timer B Available -- Available Available -- Available Available -- -- Available Available Timer C Available -- -- Available -- -- Available Available -- Available Available Timer D Available -- Available Available -- Available Available -- Available -- --
Timer A Timer A Functions Timer A has the following functions. * Free-running timer * Realtime clock time base The block diagram of timer A is shown in figure 35.
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HD404889/HD404899/HD404878/HD404868 Series
32.768-kHz oscillator 1/4 1/2 2 fW 1/2 t Wcyc Selector Internal data bus Selector Clock Timer counter A (TCA) Overflow fW t Wcyc Prescaler W (PSW)
/2 /8 / 16 / 32
Timer A interrupt request flag (IFTA)
Selector
/2 /4 /8 / 32 / 128 / 512 / 1024 / 2048
System clock
o PER
Prescaler S (PSS)
3 Timer mode register A (TMA)
Data bus Clock line Signal line
Figure 35 Timer A Block Diagram Timer A Operation Free-running timer operation: The timer A input clock is selected by timer mode register A (TMA: $00F). Timer A is reset to $00 by an MCU reset, and counts up each time the input clock is input. When the input clock is input after the timer A value reaches $FF, overflow output is generated, and the timer A value becomes $00. The generated overflow output sets the timer A interrupt request flag (IFTA: $002,0). Timer A continues counting up after the count value returns to $00, so that an interrupt is generated regularly every 256 input clock cycles. Realtime clock time base operation: Timer A can be used as the realtime clock time base by setting bit 3 (TMA3) of timer mode register A to 1. As the prescaler W output is input to timer/counter A, interrupts are generated with accurate timing using the 32.768 kHz crystal oscillator as the basic clock. When timer A is used as the realtime clock time base, prescaler W and timer/counter A can be reset to $00 by the program.
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HD404889/HD404899/HD404878/HD404868 Series
Timer A Register Timer A operation is set by means of the following register. Timer mode register A (TMA: $00F): Timer mode register A (TMA: $00F) is a 4-bit write-only register. Timer A operation and input clock selection are set as shown in figure 36.
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HD404889/HD404899/HD404878/HD404868 Series
Timer mode register A (TMA: $00F) Bit Read/Write Initial value on reset Bit name 3 W 0 TMA3 2 W 0 TMA2 1 W 0 TMA1 0 W 0 TMA0
TMA3
TMA2
TMA1 0
TMA0 0 1
Source prescaler PSS PSS PSS PSS PSS PSS PSS PSS PSW PSW PSW PSW PSW
Input clock period Operating mode 2,048 tcyc 1,024 tcyc 512 tcyc 128 tcyc 32 tcyc 8 tcyc 4 tcyc 2 tcyc 32 twcyc 16 twcyc 8 twcyc 2 twcyc 1/2 twcyc Time base mode Timer A mode
0 0 1 1 0 0 0 1 0 1 1 0 0 1 0 1 1 1 0 0 1 1 * : Don't care Notes: 1. twcyc = 244.14 s (using 32.768 kHz crystal oscillator) 2. Timer/counter overflow output period (s) = input clock period (s) x 256. 3. If PSW and TCA reset is selected during LCD, the LCD enters the halt state (power switch off). Therefore, to provide continuous LCD the PSW and TCA reset interval must be minimized by the program. 4. The division ratio must not be changed while time base mode is being used, as this will result in an error in the overflow period. 1 * 0 1
Not Used PSW, TCA reset
Figure 36 Timer Mode Register A (TMA)
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HD404889/HD404899/HD404878/HD404868 Series
Timer B Timer B Functions: Timer B has the following functions. * Free-running/reload timer * External event counter * Timer output operation (toggle output, PWM output) The block diagram of timer B is shown in figure 37.
Timer C clock source Timer output control logic 1 EVNB Edge detection logic 2 /2 /4
Prescaler S (PSS)
Timer B ineterrupt request flag (IFTB)
TOB
Timer read register BL (TRBL) 4
Selector
Timer read register BU (TRBU)
System clock
Free-runnning/Reload control
oPER
/32 /128 /512 /2048
(TCBL) 4
(TCBU) 4
Timer write register B (TWBL) (TWBU)
3
Timer mode register B1 (TMB1) 3
Timer mode register B2 (TMB2) Data bus Clock line Signal line
Figure 37 Timer B Block Diagram
Internal data bus
/8
Timer counter B
Overflow
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HD404889/HD404899/HD404878/HD404868 Series
Timer B Operation * Free-running/reload timer: Free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected by means of timer mode register B1 (TMB1). Timer B is initialized to the value written to timer write register B (TWBL, TWBU) by software, and counts up by 1 each time the input clock is input. When the input clock is input after the timer B value reaches $FF, overflow output is generated. Timer B is then set to the value in timer write register B if the reload timer function is selected, or to $00 if the free-running timer function is selected, and starts counting up again. Overflow output sets the timer B interrupt request flag (IFTB). This flag is reset by the program or by an MCU reset. For details, see figure 3, Interrupt Control Bit and Register Flag Area Configuration, and table 1, Initial Values after MCU Reset. * External event counter operation: When external event input is designated for the input clock, timer B operates as an external event counter. When external event input is used, the R1 0/EVNB pin is designated as the EVNB pin by port mode register 2 (PMR2). The external event detected edge for timer B can be designated as a falling edge, rising edge, or both falling and rising edges in the input signal by means of timer mode register B2 (TMB2). If both falling and rising edges are selected, the input signal falling and rising edge interval should be at least 2tcyc. Timer B counts up by 1 each time a falling edge is detected in the signal input at the EVNB pin. Other operations are the same as for the free-running/reload timer function. * Timer output operation: With timer B, the R13/TOB pin is designated as the TOB pin by the setting of bit 3 of port mode register 2 (PMR2), and toggle waveform output or PWM waveform output can be selected by timer mode register B2 (TMB2). Toggle output: With toggle output, the output level is changed upon input of the next clock pulse after the timer B value reaches $FF. Use of this function in combination with the reload timer allows a clock signal with any period to be output, enabling it to be used as buzzer output. The output waveform is shown in figure 38 (1). PWM output: With PWM output, variable-duty pulses are output. The output waveform is as shown in figure 38 (2), according to the contents of timer mode register B1 (TMB1) and timer write register B (TWBL, TWBU). When the waveform is output with bit 3 (TMB13) of timer mode register B1 cleared to 0, the write to timer write register B to change the duty is effective from the next frame, whereas if the waveform is output with the TMB13 bit set to 1 (reload setting), the next frame is output immediately after the timer write register write. * Module standby: With timer B, the supply of the system clock to the timer/counter can be halted by setting bit 0 of module standby register 1 (MSR1: $00D) to 1. In the module standby state, the mode register value is retained but the counter value is not guaranteed.
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HD404889/HD404899/HD404878/HD404868 Series
(1) Toggle output waveform (timer B, timer C)
Free-running timer
256 clock periods Reload timer
256 clock periods
(256 - N) clock periods
(256 - N) clock periods
(2) PWM output waveform (timer B, timer C)
T x (N + 1)
TMB13 = 0 (free-running timer) T x 256 T TMB13 = 1 (reload timer) T x (256 - N)
Notes:
T: Counter input clock period The clock input source and division ratio are controlled by timer mode register B1 and timer mode register C1. N: Value in timer write register B or timer write register C When N = 255 (= $FF), PWM output is always fixed at the timer low level.)
(
)
Figure 38 Timer Output Waveforms
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HD404889/HD404899/HD404878/HD404868 Series
Timer B Registers Timer B operation setting and timer B value reading/writing is controlled by the following registers. Timer mode register B1 (TMB1: $010) Timer mode register B2 (TMB2: $011) Timer write register B (TWBL: $012, TWBU: $013) Timer read register B (TRBL: $012, TRBU: $013) Port mode register 2 (PMR2: $00A) Module standby register 1 (MSR1: $00D) * Timer mode register B1 (TMB1: $010): Timer mode register B1 (TMB1) is a 4-bit write-only register, used to select free-running/reload timer operation and the input clock as shown in figure 39. Timer mode register B1 (TMB1) is reset to $0 by an MCU reset: A modification of timer mode register B1 (TMB1) becomes effective after execution of two instructions following the timer mode register B1 (TMB1) write instruction. The program must provide for timer B initialization by writing to timer write register B (TWBL, TWBU) to be executed after the postmodification mode has become effective.
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HD404889/HD404899/HD404878/HD404868 Series
Timer mode register B1 (TMB1: $010) Bit Read/Write Initial value on reset Bit name 3 W 0 TMB13 2 W 0 TMB12 1 W 0 TMB11 0 W 0 TMB10
TMB12
TMB11 0
TMB10 0 1
Input clock period and input clock source 2,048 tcyc 512 tcyc 128 tcyc 32 tcyc 8 tcyc 4 tcyc 2 tcyc R10/EVNB (external event input)
0 1 0 1 1
0 1 0 1 0 1
TMB13 0 1
Free-running/reload timer Free-running timer Reload timer
Figure 39 Timer Mode Register B1 (TMB1) * Timer mode register B2 (TMB2: $011): Timer mode register B2 (TMB2) is a 3-bit write-only register, used to select the timer B output mode and EVNB pin detected edge as shown in figure 40. Timer mode register B2 (TMB2) is reset to $0 by an MCU reset.
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HD404889/HD404899/HD404878/HD404868 Series
Timer mode register B2 (TMB2: $011) Bit Read/Write Initial value on reset Bit name 3 -- -- -- 2 W 0 TMB22 1 W 0 TMB21 0 W 0 TMB20
TMB21 TMB20 0 0 1 1 TMB22 0 1 0 1
EVNB pin detected edge Not detected Falling edge detection Rising edge detection Both rising and falling edge detection
Timer B output waveform Toggle output PWM output
Figure 40 Timer Mode Register B2 (TMB2) * Timer write register B (TWBL: $012, TWBU:$013): Timer write register B (TWBL, TWBU) is a write-only register composed of a lower digit (TWBL) and an upper digit (TWBU) (figures 41 and 42). The lower digit (TWBL) of timer write register B is reset to $0 by an MCU reset, while the upper digit (TWBU) is undetermined. Timer B can be initialized by writing to timer write register B (TWBL, TWBU). To write the data, first write the lower digit (TWBL). The lower digit write does not change the timer B value. Next, write the upper digit (TWBU). Timer B is then initialized to the timer write register B (TWBL, TWBU) value. When writing to timer write register B (TWBL, TWBU) from the second time onward, if it is not necessary to change the lower digit (TWBL) reload value, timer B initialization is completed by the upper digit write alone.
Timer write register B (lower) (TWBL: $012) Bit Read/Write Initial value on reset Bit name 3 W 0 TWBL3 2 W 0 TWBL2 1 W 0 TWBL1 0 W 0 TWBL0
Figure 41 Timer Write Register B (Lower) (TWBL)
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HD404889/HD404899/HD404878/HD404868 Series
Timer write register B (upper) (TWBU: $013) Bit Read/Write Initial value on reset Bit name 3 W 2 W 1 W 0 W
Undetermined Undetermined Undetermined Undetermined
TWBU3
TWBU2
TWBU1
TWBU0
Figure 42 Timer Write Register B (Upper) (TWBU) * Timer read register B (TRBL: $012, TRBU: $013): Timer read register B (TRBL, TRBU) is a read-only register composed of a lower digit (TRBL) and an upper digit (TRBU) from which the value of the upper digit of timer B is read directly (figures 43 and 44). First, read the upper digit (TRBU) of timer read register B. The current value of the timer B upper digit is read and, at the same time, the value of the timer B lower digit is latched in the lower digit (TRBL) of timer read register B. The timer B value is obtained when the upper digit (TRBU) of timer read register B is read by reading the lower digit (TRBL) of timer read register B.
Timer read register B (lower) (TRBL: $012) Bit Read/Write Initial value on reset Bit name 3 R TRBL3 2 R 1 R 0 R
Undetermined Undetermined Undetermined Undetermined
TRBL2
TRBL1
TRBL0
Figure 43 Timer Read Register B (Lower) (TRBL)
Timer read register B (upper) (TRBU: $013) Bit Read/Write Initial value on reset Bit name 3 R 2 R 1 R 0 R
Undetermined Undetermined Undetermined Undetermined
TRBU3
TRBU2
TRBU1
TRBU0
Figure 44 Timer Read Register B (Upper) (TRBU)
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HD404889/HD404899/HD404878/HD404868 Series
* Port mode register 2 (PMR2: $00A): Port mode register 2 (PMR2) is a write-only register used to set the function of the R10/EVNB and R1 3/TOB pins as shown in figure 45. Port mode register 2 (PMR2) is reset to $0 by an MCU reset.
Port mode register 2 (PMR2: $00A) Bit Read/Write Initial value on reset Bit name 3 W 0 PMR23 2 W 0 PMR22 1 W 0 PMR21* 0 W 0 PMR20
PMR20 0 1 PMR21 0 1 PMR22 0 1 PMR23 0 1
R10/EVNB pin mode selection R10 EVNB
R11/EVND pin mode selection R11 EVND
R12/BUZZ pin mode selection R12 BUZZ
R13/TOB pin mode selection R13 TOB
Note: * Applies to HD404889, HD404899, and HD404878 Series
Figure 45 Port Mode Register 2 (PMR2: $00A) * Module standby register 1 (MSR1: $00D): Module standby register 1 (MSR1) is a write-only register used to designate supply or stopping of the clock to timer B as shown in figure 46. Module standby register 1 (MSR1) is reset to $0 by an MCU reset.
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HD404889/HD404899/HD404878/HD404868 Series
Module standby register 1 (MSR1: $00D) Bit Read/Write Initial value on reset Bit name 3 -- -- -- 2 W 0 MSR12
1
W 0 MSR11
0 W 0 MSR10
MSR10 0 1 MSR11 0 1 MSR12 0 1
Timer B clock supply control Supplied Stopped
Timer C clock supply control Supplied Stopped
Timer D clock supply control Supplied Stopped
Figure 46 Module Standby Register 1 (MSR1)
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HD404889/HD404899/HD404878/HD404868 Series
Timer C Timer C Functions:Timer : C has the following functions. * Free-running/reload timer * Watchdog timer * Timer output operation (toggle output, PWM output) The block diagram of timer C is shown in figure 47.
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HD404889/HD404899/HD404878/HD404868 Series
System reset signal Watchdog on flag (WDON) TOC Timer output control logic Timer C interrupt request flag (IFTC)
Watchdog timer control logic
System clock
o PER
Timer B overflow
Timer read register CL (TRCL) 4
Timer read register CU (TRCU)
/4 /8 Prescaler (PSS) / 32 / 128 / 512 / 2048 Timer counter C Selector (TCCL) Free-running/reload control 4 (TCCU) 4
Overflow
/2
Timer write register C (TWCL) (TWCU)
3 Timer mode register C1 (TMC1)
Timer output control Data bus Clock line Signal line
Timer mode register C2 (TMC2)
Figure 47 Timer C Block Diagram
Internal data bus
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HD404889/HD404899/HD404878/HD404868 Series
Timer C Operation * Free-running/reload timer: Free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected by means of timer mode register C1 (TMC1). Timer C is initialized to the value written to timer write register C (TWCL, TWCU) by software, and counts up by 1 each time the input clock is input. When the input clock is input after the timer C value reaches $FF, overflow output is generated. Timer C is then set to the value in timer write register C (TWCL, TWCU) if the reload timer function is selected, or to $00 if the free-running timer function is selected, and starts counting up again. Overflow output sets the timer C interrupt request flag (IFTC). This flag is reset by the program or by an MCU reset. For details, see figure 3, Interrupt Control Bit and Register Flag Area Configuration, and table 1, Initial Values after MCU Reset. * 16-bit timer operation: When timer B overflow flag is selected as the clock source, timer C can be used as a 16-bit timer that counts the timer B clock source pulses. In this case, since the timer B and timer C free-running/reload settings are independent, the settings should be made to suit the purpose. * Watchdog timer operation: By using the timer C overflow output, timer C can be used as a watchdog timer for detecting program runaway. The watchdog timer is enabled when the watchdog on flag (WDON) is set to 1, and generates an MCU reset when timer C overflows. Usually, timer C initialization is performed by the program before the timer C value reaches $FF, so controlling program runaway. * Timer output operation: With timer C, the R20/TOC pin is designated as the TOC pin by setting bit 0 of port mode register 3 (PMR3) to 1, and toggle waveform output or PWM waveform output can be selected by timer mode register C2 (TMC2). Toggle output The operation is similar to that for timer B toggle output. PWM output The operation is similar to that for timer B PWM output. * Module standby: The operation is similar to that for timer B module standby.
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HD404889/HD404899/HD404878/HD404868 Series
Timer C Registers Timer C operation setting and timer C value reading/writing is controlled by the following registers. Timer mode register C1 (TMC1: $014) Timer mode register C2 (TMC2: $015) Timer write register C (TWCL: $016, TWCU: $017) Timer read register C (TRCL: $016, TRCU: $017) Port mode register 3 (PMR3: $00B) Module standby register 1 (MSR1: $00D) * Timer mode register C1 (TMC1: $014): Timer mode register C1 (TMC1) is a 4-bit write-only register, used to select free-running/reload timer operation, the input clock, and the prescaler division ratio as shown in figure 48. Timer mode register C1 (TMC1) is reset to $0 by an MCU reset. A modification of timer mode register C1 (TMC1) becomes effective after execution of two instructions following the timer mode register C1 (TMC1) write instruction. The program must provide for timer C initialization by writing to timer write register C (TWCL, TWCU) to be executed after the postmodification mode has become effective.
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Timer mode register C1 (TMC1: $014) Bit Read/Write Initial value on reset Bit name 3 W 0 TMC13 2 W 0 TMC12 1 W 0 TMC11 0 W 0 TMC10
TMC12
TMC11 0
TMC10 0 1 0
Input clock period 2,048 tcyc 512 tcyc 128 tcyc 32 tcyc 8 tcyc 4 tcyc 2 tcyc Timer B overflow
0 1
1 0
0 1 1
1 0 1
TMC13 0 1
Free-running/reload timer Free-running timer Reload timer
Figure 48 Timer Mode Register C1 (TMC1)
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HD404889/HD404899/HD404878/HD404868 Series
* Timer mode register C2 (TMC2: $015): Timer mode register C2 (TMC2) is a 1-bit write-only register, used to select the timer C output mode as shown in figure 49. Timer mode register C2 (TMC2) is reset to $0 by an MCU reset.
Timer mode register C2 (TMC2: $015) Bit Read/Write Initial value on reset Bit name 3 -- -- -- 2 W 0 TMC22 1 -- -- -- 0 -- -- --
TMC22 0 1
Timer C output waveform Toggle output PWM output
Figure 49 Timer Mode Register C2 (TMC2) * Timer write register C (TWCL: $016, TWCU: $017): Timer write register C (TWCL, TWCU) is a write-only register composed of a lower digit (TWCL) and an upper digit (TWCU) (figures 50 and 51). Timer write register C (TWCL, TWCU) operation is similar to that for timer write register B (TWBL, TWBU).
Timer write register C (lower) (TWCL: $016) Bit Read/Write Initial value on reset Bit name 3 W 0 TWCL3 2 W 0 TWCL2 1 W 0 TWCL1 0 W 0 TWCL0
Figure 50 Timer Write Register C (Lower) (TWCL)
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HD404889/HD404899/HD404878/HD404868 Series
Timer write register C (upper) (TWCU: $017) Bit Read/Write Initial value on reset Bit name 3 W 2 W 1 W 0 W
Undetermined Undetermined Undetermined Undetermined TWCU3 TWCU2 TWCU1 TWCU0
Figure 51 Timer Write Register C (Upper) (TWCU) * Timer read register C (TRCL: $016, TRCU: $017): Timer read register C (TRCL, TRCU) is a read-only register composed of a lower digit (TRCL) and an upper digit (TRCU) from which the value of the upper digit of timer C is read directly (figures 52 and 53). Timer read register C (TRCL, TRCU) operation is similar to that for timer read register B (TRBL, TRBU).
Timer read register C (upper) (TRCL: $016) Bit Read/Write Initial value on reset Bit name 3 R 2 R 1 R 0 R
Undetermined Undetermined Undetermined Undetermined TRCL3 TRCL2 TRCL1 TRCL0
Figure 52 Timer Read Register C (Lower) (TRCL)
Timer read register C (upper) (TRCU: $017) Bit Read/Write Initial value on reset Bit name 3 R 2 R 1 R 0 R
Undetermined Undetermined Undetermined Undetermined TRCU3 TRCU2 TRCU1 TRCU0
Figure 53 Timer Read Register C (Upper) (TRCU)
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HD404889/HD404899/HD404878/HD404868 Series
* Port mode register 3 (PMR3: $00B): Port mode register 3 (PMR3) is a write-only register used to set the function of the R20/TOC pin as shown in figure 54. Port mode register 3 (PMR3) is reset to $0 by an MCU reset.
Port mode register 3 (PMR3: $00B) Bit Read/Write Initial value on reset Bit name 3 W 0 PMR33 2 W 0 PMR32 1 W 0 PMR31 0 W 0 PMR30
PMR30 0 1 PMR31 0 1 PMR33 0 1 PMR32 0 1 : Don't care
R20/TOC pin mode selection R20 TOC
R21/SCK pin mode selection R21 SCK
R22/SI/SO pin mode selection R22 SI SO
Figure 54 Port Mode Register 3 (PMR3) * Module standby register 1 (MSR1: $00D): Module standby register 1 (MSR1) is a write-only register used to designate supply or stopping of the clock to timer C as shown in figure 46. Module standby register 1 (MSR1) is reset to $0 by an MCU reset.
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Timer D (HD404889/HD404899/HD404878 Series) Timer D functions : Timer D has the following functions. * Free-running/reload timer * External event counter * Input capture timer Block diagrams of timer D in different operating modes are shown in figures 55-1 and 55-2.
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Timer D interrupt request flag (IFTD) EVND Edge detection logic
System clock
oPER Timer read register DL (TRDL) /2 Prescaler S (PSS) /4 / 32 / 128 / 512 / 2048 Selector /8 4
Timer read register DU (TRDU)
(TCDL) Free-running/ reload control 4
(TCDU) 4
Timer write register D (TWDL) (TWDU)
3 Timer mode register D1 (TMD1) 2
Edge detection control Data bus Clock line Signal line
Timer mode register D2 (TMD2)
Figure 55-1 Timer D Block Diagram (Reload Timer and Event Counter Modes)
Internal data bus
Timer counter D
Overflow
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HD404889/HD404899/HD404878/HD404868 Series
Input capture status flag (ICSF) Input capture error flag (ICEF) Timer D interrupt request flag (IFTD)
EVND
Edge detection logic
Read signal
2 System clock oPER Timer read register D (TRDL) /2 Prescaler S (PSS) /4 /32 /128 /512 /2048 Selector /8 Timer counter D (TCDL) (TCDU) Input capture timer control 4 (TRDU) 4
Overflow
3 3 Time mode register D1 (TMD1)
Timer mode register D2 (TMD2)
Data bus Clock line Signal line
Figure 55-2 Timer D Block Diagram (Input Capture Timer Mode)
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HD404889/HD404899/HD404878/HD404868 Series
Timer D Operation * Free-running/reload timer: Free-running/reload timer operation, the input clock source, and the prescaler division ratio are selected by means of timer mode register D1 (TMD1). Timer D is initialized to the value written to timer write register D (TWDL, TWDU) by software, and counts up by 1 each time the input clock is input. When the input clock is input after the timer D value reaches $FF, overflow output is generated. Timer D is then set to the value in timer write register D (TWDL, TWDU) if the reload timer function is selected, or to $00 if the free-running timer function is selected, and starts counting up again. Overflow output sets the timer D interrupt request flag (IFTD). This flag is reset by the program or by an MCU reset. For details, see figure 3, Interrupt Control Bit and Register Flag Area Configuration, and table 1, Initial Values after MCU Reset. * External event counter operation: When external event input is designated for the input clock, timer D operates as an external event counter. When external event input is used, the R1 1/EVND pin is designated as the EVND pin by port mode register 2 (PMR2). The external event detected edge for timer D can be designated as a falling edge, rising edge, or both falling and rising edges in the input signal by means of timer mode register D2 (TMD2). If both falling and rising edges are selected, the input signal falling and rising edge interval should be at least 2tcyc. Timer D counts up by 1 each time the edge selected by timer mode register D2 (TMD2) is detected. Other operations are the same as for the free-running/reload timer function. * Input capture timer operation: The input capture timer function is used to measure the time between trigger input edges input at the EVND pin. The trigger input edge can be designated as a falling edge, rising edge, or both falling and rising edges by means of timer mode register D2 (TMD2). When a trigger input edge is detected at the EVND pin, the current timer D value is stored in timer read register D (TRDL, TRDU), and the timer D interrupt request flag (IFTD) and input capture status flag (ICSF) are set. At the same time, timer D is reset to $00 and continues counting up. If the next trigger input edge is input while the input capture status flag (ICSF) is set, or if timer D overflows, the input capture error flag (ICEF) is set. The input capture status flag (ICSF) and input capture error flag (ICEF) are reset to 0 by an MCU reset or by writing 0 to them. When timer D is set to operate as an input capture timer, it is reset to $00.
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Timer D Registers: Timer D operation setting and timer D value reading/writing is controlled by the following registers. Timer mode register D1 (TMD1: $018) Timer mode register D2 (TMD2: $019) Timer write register D (TWDL: $01A, TWDU: $01B) Timer read register D (TRDL: $01A, TRDU: $01B) Port mode register 2 (PMR2: $00A) Module standby register 1 (MSR1: $00D) * Timer mode register D1 (TMD1: $018): Timer mode register D1 (TMD1) is a 4-bit write-only register, used to select free-running/reload timer operation, the input clock, and the prescaler division ratio as shown in figure 56. Timer mode register D1 (TMD1) is reset to $0 by an MCU reset. A modification of timer mode register D1 (TMD1) becomes effective after execution of two instructions following the timer mode register D1 (TMD1) write instruction. The program must provide for timer D initialization by writing to timer write register D (TWDL, TWDU) to be executed after the post-modification mode has become effective. When timer D is set to operate as an input capture timer, an internal clock should be set as the input clock.
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Timer mode register D1 (TMD1: $018) Bit Read/Write Initial value on reset Bit name 3 W 0 TMD13 2 W 0 TMD12 1 W 0 TMD11 0 W 0 TMD10
TMD12
TMD11 0
TMD10 0 1
Input clock period and input clock source 2,048 tcyc 512 tcyc 128 tcyc 32 tcyc 8 tcyc 4 tcyc 2 tcyc R11/EVND (external event input)
0 1 0 1 1 TMD13 0 1
0 1 0 1 0 1
Free-running/reload timer Free-running timer Reload timer
Figure 56 Timer Mode Register D1 (TMD1) * Timer mode register D2 (TMD2: $019): Timer mode register D2 (TMD2) is a 3-bit write-only register, used to select the EVND pin detected edge and input capture operation as shown in figure 57. Timer mode register D2 (TMD2) is reset to $0 by an MCU reset.
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Timer mode register D2 (TMD2: $019) Bit Read/Write Initial value on reset Bit name 3 -- -- -- 2 W 0 TMD22 1 W 0 TMD21 0 W 0 TMD20
TMD21 0
TMD20 0 1
EVND pin detected edge Not detected Falling edge detection Rising edge detection Both rising and falling edge detection
1
0 1
TMD22 0 1
Input capture setting Free-running/reload timer Input capture timer
Figure 57 Timer Mode Register D2 (TMD2) * Timer write register D (TWDL: $01A, TWDU: $01B): Timer write register D (TWDL, TWDU) is a write-only register composed of a lower digit (TWDL) and an upper digit (TWDU) (figures 58 and 59). Timer write register D (TWDL, TWDU) operation is similar to that for timer write register B (TWBL, TWBU).
Timer write register D (lower) (TWDL: $01A)
Bit Read/Write Initial value on reset Bit name
3 W 0 TWDL3
2 W 0 TWDL2
1 W 0 TWDL1
0 W 0 TWDL0
Figure 58 Timer Write Register D (Lower) (TWDL)
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Timer write register D (upper) (TWDU: $01B)
Bit Read/Write Initial value on reset Bit name
3 W
2 W
1 W
0 W
Undetermined Undetermined Undetermined Undetermined TWDU3 TWDU2 TWDU1 TWDU0
Figure 59 Timer Write Register D (Upper) (TWDU) * Timer read register D (TRDL: $01A, TRDU: $01B): Timer read register D (TRDL, TRDU) is a read-only register composed of a lower digit (TRDL) and an upper digit (TRDU) (figures 60 and 61). Timer read register D (TRDL, TRDU) operation is similar to that for timer read register B (TRBL, TRBU). In the input capture timer operating mode, when the timer D value is read after trigger input, it does not matter whether the lower or upper digit is read first.
Timer read register D (lower) (TRDL: $01A) Bit Read/Write Initial value on reset Bit name 3 R 2 R 1 R 0 R
Undetermined Undetermined Undetermined Undetermined TRDL3 TRDL2 TRDL1 TRDL0
Figure 60 Timer Read Register D (Lower) (TRDL)
Timer read register D (upper) (TRDU: $01B) Bit Read/Write Initial value on reset Bit name 3 R 2 R 1 R 0 R
Undetermined Undetermined Undetermined Undetermined TRDU3 TRDU2 TRDU1 TRDU0
Figure 61 Timer Read Register D (Upper) (TRDU)
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* Port mode register 2 (PMR2: $00A): Port mode register 2 (PMR2) is a write-only register used to set the R11/EVND pin function as shown in figure 45. Port mode register 2 (PMR2) is reset to $0 by an MCU reset. * Module standby register 1 (MSR1: $00D): Module standby register 1 (MSR1) is a write-only register used to designate supply or stopping of the clock to timer D as shown in figure 46. Module standby register 1 (MSR1) is reset to $0 by an MCU reset.
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Serial Interface
The serial interface serially transfers and receives 8-bit data, and includes the following features. * Multiple transmit clock sources External clock Internal prescaler output clock System clock * Output level control in idle states Five registers, an octal counter, and a multiplexer are also configured for the serial interface as follows. * * * * * * Serial data register (SRL: $026, SRU: $027) Serial mode register 1 (SMR1: $024) Serial mode register 2 (SMR2: $025) Port mode register 3 (PMR3: $00B) Octal counter (OC) Selector
The block diagram of the serial interface is shown in figure 62.
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Serial interrupt request flag (IFS)
Octal counter (OC)
SI/SO
Idle control logic
SCK
I/O control logic
Clock
Serial data register (SRL/U) Internal data bus Transfer control
2 4
1/2
PrescalerS (PSS)
/2 /8 /32 /128 /512 /2048
1/2 Selector Serial mode register 1 (SMR1)
Selector
System clock
oPER
Data bus Clock line Signal line
Serial mode register 2 (SMR2)
Figure 62 Serial Interface Block Diagram
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HD404889/HD404899/HD404878/HD404868 Series
Serial Interface Operation Selecting and changing serial interface operating mode: The operating modes that can be selected for the serial interface are shown in table 26. The combination of port mode register 3 (PMR3) values should be selected from this table. When the serial interface operating mode is changed, the serial interface internal state must be initialized by writing to serial mode register 1 (SMR1). Note : The serial interface is initialized by writing to serial mode register 1 (SMR1: $024). See serial mode register 1 for details. Table 26 Serial Interface Operating Modes
PMR3 Bit3 0 1 1 *: Don't care Bit2 * 0 1 Bit1 1 1 1 Clock continuous output mode Receive mode Transmit mode Serial interface operating mode
Serial interface pin setting: The R2 1/SCK pin and R22/SI/SO pin are set by writing data to port mode register 3 (PMR3). See serial interface registers for details. Serial clock source setting: The serial clock is set by writing data to serial mode register 1 (SMR1). See serial interface registers for details. Serial data setting: Transmit serial data is set by writing data to the serial data register (SRL, SRU). Receive serial data is obtained by reading the serial data register (SRL, SRU). Serial data is shifted by means of the serial clock to perform input/output from/to an external device. The output level of the SO pin is undetermined until the first data is output after a reset by the MCU, or until high/low control is performed in the idle state. Transfer control: Serial interface operation is started by an STS instruction. The octal counter is reset to 000 by the STS instruction, and is incremented by 1 on each rise of the serial clock. When 8 serial clock pulses have been input, or if data transmission/reception is suspended midway, the octal counter is reset to 000, the serial interrupt request flag (IFS) is set, and transfer is terminated. The serial clock is selected by means of serial mode register 1 (SMR1). See figure 66.
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Serial interface operating states: The serial interface has the operating states shown in figure 63 in external clock mode and internal clock mode. STS instruction wait state Serial clock wait state Transfer state Clock continuous output state (internal clock mode only) * STS instruction wait state Upon MCU reset ((00) and (10) in figure 63), the serial interface enters the STS instruction wait state. In the STS instruction wait state, the internal state of the serial interface is initialized. Even if the serial clock is input at this time, the serial interface will not operate. When the STS instruction is executed ((01), (11)), the serial interface enters the serial clock wait state. * Serial clock wait state The serial clock wait state is the interval from STS instruction execution until the first serial clock falling edge. When the serial clock is input in the serial clock wait state ((02), (12)), the octal counter begins counting, the contents of the serial data register (SRL) begin shifting, and the serial interface enters the transfer state. However, if clock continuous output mode is selected in internal clock mode, the serial interface enters the clock continuous output state ((17)) instead of the transfer state. If a write to serial mode register 1 (SMR1) is performed in the serial clock wait state, the serial interface enters the STS instruction wait state ((04), (14)). * Transfer state The transfer state is the interval from the first serial clock falling edge until the eighth serial clock rising edge. In the transfer state, if an STS instruction is executed or if eight serial clocks have been input, the octal counter is cleared to 000, and the serial interface makes a state transition. If an STS instruction is executed ((05), (15)), the serial interface enters the serial clock wait state. After eight serial clocks have been input, the serial interface enters the serial clock wait state ((03)) when in external clock mode, and enters the STS instruction wait state ((13)) when in internal clock mode. In internal clock mode, the serial clock stops after output of eight clocks. If a write to serial mode register 1 (SMR1) is performed in the transfer state ((06), (16)), the serial interface is initialized and enters the STS instruction wait state. When the serial interface switches from the transfer state to another state, the octal counter is reset to 000 and the serial interrupt request flag (IFS) is set. * Clock continuous output state (internal clock mode only) In the clock continuous output state, no receive or transmit operation is performed, and the serial clock is only output from the SCK pin. It is therefore effective in internal clock mode. If the serial clock is input ((17)) when bit 3 (PMR33) of port mode register 3 (PMR3) is cleared to 0 and the serial interface is in the serial clock wait state, a transition is made to the clock continuous output state. If a write to serial mode register 1 (SMR1) is performed in the clock continuous output state ((18)), the serial interface enters the STS instruction wait state.
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MCU reset (00) STS instruction wait state (octal counter ="000", serial clock disabled)
SMR1 write (04) STS instruction (01)
SMR1 write (06) (IFS "1")
Serial clock (02) Serial clock wait state (octal counter ="000") 8 serial clocks (03) STS instruction (05) (IFS "1") External clock mode Transfer state (octal counter "000")
MCU reset (10) SMR1 write (18)
STS instruction wait state (octal counter ="000", serial clock disabled)
Clock continuous output state (PMR33 ="0") SMR1 write (14) Serial clock (17) Serial clock (12) Serial clock wait state (octal counter ="000") STS instruction (15) (IFS"1") Internal clock mode ( ) Refer to the text for details on the circled numbers in the figure. STS instruction (11)
8 serial clocks (13) SMR1 write (16) (IFS"1")
Transfer state (octal counter "000")
Figure 63 Serial Interface Operating States
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Idle high/low control: When the serial interface is in the STS instruction wait state or the serial clock wait state (i.e. when idle), the output level of the SO pin can be set arbitrarily by software. Idle high/low control is performed by writing the output level to bit 1 (SMR21) of serial mode register 2 (SMR2). An example of idle high/low control is shown in figure 64. Idle high/low control cannot be performed in the transfer state.
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Serial clock wait state State MCU reset PMR3 write SMR1 write SMR2 write SRL, SRU write STS instruction SCK pin (input) SO pin Undefined Idle
LSB
Serial clock wait state Transfer state STS wait state
STS wait state
Port setting External clock setting Idle H/L setting Transmit data write Dummy write to cause state transition Idle H/L setting
MSB
Idle
IFS (1) External clock mode (Flag reset by transfer completion processing)
Serial clock wait state State MCU reset PMR3 write SMR1 write SMR2 write SRL, SRU write STS instruction SCK pin (output) SO pin Undefined Idle
LSB
STS wait state
Transfer state
STS wait state
Port setting External clock setting Idle H/L setting Transmit data write Idle H/L setting
MSB
Idle
IFS (2) Internal clock mode (Flag reset by transfer completion processing)
Figure 64 Examples of Serial Interface Operation Sequence
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Serial clock error detection (external clock mode): The serial interface will operate incorrectly in the transfer state if external noise results in unnecessary pulses being added to the serial clock. Serial clock error detection in such cases is carried out as shown in figure 65. If more than eight serial clock pulses are input due to external noise while in the transfer state, at the eighth clock pulse (including any external noise pulses), the octal counter is cleared to 000 and the serial interrupt request flag (IFS) is set. At the same time, the serial interface exits the transfer state and enters the serial clock wait state, but returns to the transfer state at the next regular clock pulse falling edge. Meanwhile, in the interrupt handling routine, transfer end processing is performed, the serial interrupt request flag is reset, and a dummy write is performed into serial mode register 1 (SMR1). The serial interface then returns to the STS wait state, and the serial interrupt request flag (IFS) is set again. It is therefore possible to detect a serial clock error by testing the serial interrupt request flag after the dummy write to serial mode register 1. Usage notes: * Initialization after register modification If a port mode register 3 (PMR3) write is performed in the serial clock wait state or transfer state, a serial mode register 1 (SMR1) write should be performed again to initialize the serial interface. * Serial interrupt request flag (IFS:$023, 2) setting If a serial mode register 1 (SMR1) write or STS instruction is executed during the first low-level interval of the serial clock in the transfer state, the serial interrupt request flag (IFS) will not be set. To ensure that the serial interrupt request flag (IFS) is properly set in this case, programming is required to make sure that the SCK pin is in the 1 state (by executing an input instruction for the R2 port) before executing a serial mode register 1 (SMR1) write or an STS instruction.
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Transfer end (IFS"1")
Disable interrupts
IFS"0"
SMR1 write
Yes IFS=1? No Normal termination
Serial clock error processing
(1) Serial clock error detection flowchart
Serial clock wait state State SCK pin (input)
Serial clock wait state Transfer state Transfer state
(Noise) 1 2 3 4 5 6 7 8
Because the serial interface returns to the transfer state, a write to SMR1 resets IFS.
SMR1 write
IFS Flag set by octal counter reaching 000 (2) Serial clock error detection sequence Flag reset by transfer end processing
Figure 65 Example of Serial Clock Error Detection
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Serial Interface Registers Serial interface operation setting and serial data reading/writing is controlled by the following registers. Serial mode register 1 (SMR1: $024) Serial mode register 2 (SMR2: $025) Serial data register (SRL: $026, SRU: $027) Port mode register 3 (PMR3: $00B) Module standby register 2 (MSR2: $00E) Serial mode register 1 (SMR1: $024): Serial mode register 1 (SMR1) has the following functions. See figure 66. * Serial clock selection * Prescaler division ratio selection * Serial interface initialization The serial mode register 1 (SMR1) is a 4-bit write-only register, and is reset to $0 by an MCU reset. A write to serial mode register 1 (SMR1) halts the supply of the serial clock to the serial data register (SRL, SRU) and the octal counter, and resets the octal counter to 000. Therefore, if serial mode register 1 (SMR1) is written to during serial interface operation, data transmission/reception will be suspended and the serial interrupt request flag (IFS) will be set. A modification of serial mode register 1 (SMR1) becomes effective after execution of two instructions following the serial mode register 1 (SMR1) write instruction. The program must therefore provide for the STS instruction to be executed two cycles after the instruction that writes to serial mode register 1 (SMR1).
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Serial mode register 1 (SMR1: $024) Bit Read/Write Initial value on reset Bit name 3 W 0 2 W 0 1 W 0 0 W 0
SMR13 SMR12 SMR11 SMR10
SMR13 SMR12 SMR11 SMR10 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0
Serial clock Serial clock SCK pin Serial clock source (PSS division ratio / 2 or 4) cycle Output Output Output Output Output Output Output Input Output Output Output Output Output Output Output Input PSS PSS PSS PSS PSS PSS System clock External clock PSS PSS PSS PSS PSS PSS System clock External clock (oPER/2048)/4 (oPER/512)/4 (oPER/128)/4 (oPER/32)/4 (oPER/8)/4 (oPER/2)/4 oPER 8192 tcyc 2048 tcyc 512 tcyc 128 tcyc 32 tcyc 8 tcyc tcyc (oPER/2048)/2 (oPER/512)/2 (oPER/128)/2 (oPER/32)/2 (oPER/8)/2 (oPER/2)/2 oPER 4096 tcyc 1024 tcyc 256 tcyc 64 tcyc 16 tcyc 4 tcyc tcyc
Figure 66 Serial Mode Register 1 (SMR1) Serial mode register 2 (SMR2: $025): Serial mode register 2 (SMR2) has the following functions. See figure 67. * R2 2/SI/SO pin PMOS control * Idle high/low control Serial mode register 2 (SMR2) is a 2-bit write-only register. The register value cannot be modified in the transfer state. Bit 2 (SMR22) of serial mode register 2 (SMR2) controls the on/off status of the R22/SI/SO pin PMOS. The bit 2 (SMR22) only is reset to 0 by an MCU reset.
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Bit 1 (SMR21) of serial mode register 2 (SMR2) performs SO pin high/low control in the idle state. The SO pin changes at the same time as the high/low write.
Serial mode register 2 (SMR2: $025) Bit Read/Write Initial value on reset Bit name 3 -- -- -- 2 W 0 1 W
undeternined
0 -- --
SMR22 SMR21
SMR21 0 1 SMR22 0 1
Idle high/low control SO pin set to low-level output in idle state SO pin set to high-level output in idle state
R22/SI/SO pin output buffer control PMOS active PMOS off (NMOS open-drain output)
Figure 67 Serial Mode Register 2 (SMR2) Serial data register (SRL: $026, SRU: $027): The serial data register (SRL, SRU) has the following functions. See figures 68 and 69. * Transmit data write and shift operations * Receive data shift and read operations The data written to the serial data register (SRL, SRU) is output LSB-first from the SO pin in synchronization with the falling edge of the serial clock. External data input LSB-first from the SI pin is latched in synchronization with the rising edge of the serial clock. Figure 70 shows the serial clock and data input/output timing chart. Writing and reading of the serial data register (SRL, SRU) must be performed only after data transmission/reception is completed. The data contents are not guaranteed if a read or write is performed during data transmission or reception.
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Serial data register (lower) (SRL: $026) Bit Read/Write Bit name 3 R/W SR3 2 R/W SR2 1 R/W SR1 0 R/W SR0
Initial value on reset Undetermined Undetermined Undetermined Undetermined
Figure 68 Serial Data Register (SRL)
Serial data register (upper) (SRU: $027) Bit Read/Write Bit name 3 R/W SR7 2 R/W SR6 1 R/W SR5 0 R/W SR4
Initial value on reset Undetermined Undetermined Undetermined Undetermined
Figure 69 Serial Data Register (SRU)
Serial clock 1 Serial output data Serial input data latch timing LSB 2 3 4 5 6 7 8 MSB
Figure 70 Serial Interface Input/Output Timing Chart
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Port mode register 3 (PMR3: $00B): Port mode register 3 (PMR3) has the following functions. See figure 71. * R2 1/SCK pin selection * R2 2/SI/SO pin selection Port mode register 3 (PMR3) is a 4-bit write-only register used to select serial interface pin settings as shown in figure 71. It is reset to $0 by an MCU reset.
Port mode register 3 (PMR3: $00B) Bit Read/Write Initial value on reset Bit name 3 W 0 2 W 0 1 W 0 0 W 0
PMR33 PMR32 PMR31 PMR30
PMR30 R20/TOC pin mode selection 0 1 R20 TOC
PMR31 R21/SCK pin mode selection 0 1 R21 SCK
PMR33 PMR32 R22/SI/SO pin mode selection 0 1 * 0 1 R22 SI SO
* : Don't care
Figure 71 Port Mode Register 3 (PMR3)
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HD404889/HD404899/HD404878/HD404868 Series
Module standby register 2 (MSR2: $00E): Module standby register 2 (MSR2) is a write-only register used to designate supply or stopping of the clock to the serial interface as shown in figure 72. Module standby register 2 (MSR2) is reset to $0 by an MCU reset.
Module standby register 2 (MSR2: $00E) Bit Read/Write Initial value on reset Bit name 3 -- -- -- 2 -- -- -- 1 W 0 0 W 0
MSR21 MSR20
MSR20 Serial clock supply control 0 1 Supplied Stopped
MSR21 A/D clock supply control 0 1 Supplied Stopped
Figure 72 Module Standby Register 2 (MSR2)
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HD404889/HD404899/HD404878/HD404868 Series
A/D Converter
HD404889 Series The MCU has a built-in successive approximation type A/D converter using a resistance ladder method, capable of digital conversion of six analog inputs with an 8-bit resolution. The A/D converter block diagram is shown in figure 73. The A/D converter comprises the following four registers. * * * * A/D mode register (AMR: $028) A/D start flag (ADSF: $020,2) A/D data register (ADRL: $02A, ADRU: $02B) Module standby register 2 (MSR2: $00E)
Note : Address $029 is a reserved register, and should not be read or written to.
Interrupt flag (IFAD)
Encoder
A/D data register (ADRU, ADRL)
3
Internal data bus
R70/AN0 R71/AN1 R72/AN2 R73/AN3 R80/AN4 R81/AN5
Selector
A/D mode register (AMR)
+
COMP
-
A/D control logic
Conversion time control
AVCC
Reference voltage
Reference voltage control
A/D start flag (ADSF) Operating mode signal (set to 1 in stop, watch, and subactive modes, and during module standby)
AVSS
D/A
Figure 73 A/D Converter Block Diagram
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HD404889/HD404899/HD404878/HD404868 Series
A/D mode register (AMR: $028): The A/D mode register is a 4-bit write-only register that shows the A/D converter speed setting and information on the analog input pin specification. The A/D conversion time is selected by bit 0, and the channel by bits 1, 2, and 3 (figure 74). A/D start flag (ADSF: $020,2): A/D conversion is started by writing 1 to the A/D start flag. When conversion ends, the converted data is placed in the A/D data register and the A/D start flag is cleared at the same time. (figure 75).
A/D mode register (AMR: $028) Bit Read/Write Initial value on reset Bit name 3 W 0 AMR3 2 W 0 AMR2 1 W 0 AMR1 0 W 0 AMR0
AMR0 A/D conversion time 0 1 65 tcyc 125 tcyc
AMR3 AMR2 AMR1 Analog input channel selection 0 0 1 * 0 1 0 1 1 0 1 0 1 * : Don't care No selection AN0 AN1 AN2 AN3 AN4 AN5
Figure 74 A/D Mode Register (AMR)
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HD404889/HD404899/HD404878/HD404868 Series
A/D start flag (ADSF: $020,2) Bit Read/Write Initial value on reset Bit name 3 R/W 0 DTON 2 R/W 0 ADSF 1 R/W 0 WDON 0 R/W 0 LSON
LSON (see low-power mode section) WDON (see timer section) A/D start flag (ADSF) 1 0 A/D conversion starts Indicates end of A/D conversion
DTON (see low-power mode section)
Figure 75 A/D Start Flag (ADSF) A/D data register (ADRL: $02A, ADRU: $02B): The A/D data register is a read-only register consisting of a lower and upper 4 bits. This register is not cleared by a reset. Also, data read during A/D conversion is not guaranteed. At the end of A/D conversion, the resulting 8-bit data is stored in this register, and is held until the next conversion operation starts (figures 76, 77, and 78).
ADRU : $02B 3 2 1 0 3
ADRL : $02A 2 1 0
MSB bit7
LSB bit0
Conversion result
Figure 76 A/D Data Register
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HD404889/HD404899/HD404878/HD404868 Series
A/D data register-lower (ADRL: $02A) Bit Read/Write Initial value on reset Bit name 3 R 1 ADRL3 2 R 1 ADRL2 1 R 1 ADRL1 0 R 1 ADRL0
Figure 77 A/D Data Register-Lower (ADRL)
A/D data register-upper (ADRU: $02B) Bit Read/Write Initial value on reset Bit name 3 R 0 ADRU3 2 R 1 ADRU2 1 R 1 ADRU1 0 R 1 ADRU0
Figure 78 A/D Data Register-Upper (ADRU) Module standby register 2 (MSR2: $00E): Writing 1 to bit 1 of module standby register 2 stops the supply of the system clock to the A/D module and cuts the current (IAD ) flowing in the ladder resistor. Usage notes: * * * * Use the SEM or SEMD instruction to write to the A/D start flag (ADSF). Do not write to the ADSF during A/D conversion. Data in the A/D data register is undetermined during A/D conversion. As the A/D converter operates on a clock from OSC, it stops in stop mode, watch mode, and subactive mode. The current flowing in the A/D converter ladder resistor is also cut in these low-power modes to reduce power consumption. * When an analog input pin is selected by the A/D mode register, the pull-up MOS for that pin is disabled.
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HD404889/HD404899/HD404878/HD404868 Series
A/D Converter
HD404899/HD404868 Series The MCU has a built-in successive approximation type A/D converter using a resistance ladder method, capable of digital conversion of six analog inputs (four analog inputs in the HD404868 Series) with a 10-bit resolution. The A/D converter block diagram is shown in figures 79-1 and 79-2. The A/D converter comprises the following four registers. * * * * A/D mode register (AMR: $028) A/D start flag (ADSF: $020,2) A/D data register (ADRL: $029, ADRM: $02A, ADRU: $02B) Module standby register 2 (MSR2: $00E)
Interrupt flag (IFAD)
Encoder
A/D data register (ADRU, ADRM, ADRL)
3
Internal data bus
R70/AN0 R71/AN1 R72/AN2 R73/AN3 R80/AN4 R81/AN5
Selector
A/D mode register (AMR)
+
COMP
-
A/D control logic
Conversion time control
AVCC
Reference voltage
Reference voltage control
A/D start flag (ADSF) Operating mode signal (set to 1 in stop, watch, and subactive modes, and during module standby)
AVSS
D/A
Figure 79-1 A/D Converter Block Diagram (HD404899 Series)
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HD404889/HD404899/HD404878/HD404868 Series
Interrupt flag (IFAD)
Encoder
A/D data register (ADRU, ADRM, ADRL)
3
Internal data bus
R70/AN0 R71/AN1 R72/AN2 R73/AN3
Selector
A/D mode register (AMR)
+
COMP
-
A/D control logic
Conversion time control
VCC
Reference voltage
Reference voltage control
A/D start flag (ADSF) Operating mode signal (set to 1 in stop, watch, and subactive modes, and during module standby)
GND
D/A
Figure 79-2 A/D Converter Block Diagram (HD404868 Series)
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HD404889/HD404899/HD404878/HD404868 Series
A/D mode register (AMR: $028): The A/D mode register is a 4-bit write-only register that shows the A/D converter speed setting and information on the analog input pin specification. The A/D conversion time is selected by bit 0, and the channel by bits 1, 2, and 3 (figure 80). A/D start flag (ADSF: $020,2): A/D conversion is started by writing 1 to the A/D start flag. When conversion ends, the converted data is placed in the A/D data register and the A/D start flag is cleared at the same time. (figure 81).
A/D mode register (AMR: $028) Bit Read/Write Initial value on reset Bit name 3 W 0 AMR3 2 W 0 AMR2 1 W 0 AMR1 0 W 0 AMR0
AMR0 A/D conversion time 0 1 65 tcyc 125 tcyc
AMR3 AMR2 AMR1 Analog input channel selection 0 0 1 0 1 0 1 1 0 1 0 1 Note: * Applies to HD404899 Series. No selection AN0 AN1 AN2 AN3 AN4* AN5*
Figure 80 A/D Mode Register (AMR)
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HD404889/HD404899/HD404878/HD404868 Series
A/D start flag (ADSF: $020,2) Bit Read/Write Initial value on reset Bit name 3 R/W 0 DTON 2 R/W 0 ADSF 1 R/W 0 WDON 0 R/W 0 LSON
LSON (see low-power mode section) WDON (see timer section) A/D start flag (ADSF) 1 0 A/D conversion starts Indicates end of A/D conversion
DTON (see low-power mode section)
Figure 81 A/D Start Flag (ADSF) A/D data register (ADRL: $029, ADRM: $02A, ADRU: $02B): The A/D data register is a read-only register consisting of a middle and upper 4 bits. This register is not cleared by a reset. Also, data read during A/D conversion is not guaranteed. At the end of A/D conversion, the resulting 10-bit data is stored in this register, and is held until the next conversion operation starts (figures 82, 83, 84 and 85).
ADRU : $02B 3 2 1 0 3 ADRM : $02A 2 1 0 ADRL : $029 3 2
MSB bit9
LSB bit0
Conversion result
Figure 82 A/D Data Register
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HD404889/HD404899/HD404878/HD404868 Series
A/D data register-lower (ADRL: $029) Bit Read/Write Initial value on reset Bit name 3 R 1 ADRL3 2 R 1 ADRL2 1 -- -- Not used 0 -- -- Not used
Figure 83 A/D Data Register-Lower (ADRL)
A/D data register-middle (ADRM: $02A) Bit Read/Write Initial value on reset Bit name 3 R 1 ADRM3 2 R 1 ADRM2 1 R 1 ADRM1 0 R 1 ADRM0
Figure 84 A/D Data Register-Middle (ADRM)
A/D data register-upper (ADRU: $02B) Bit Read/Write Initial value on reset Bit name 3 R 0 ADRU3 2 R 1 ADRU2 1 R 1 ADRU1 0 R 1 ADRU0
Figure 85 A/D Data Register-Upper (ADRU) Module standby register 2 (MSR2: $00E): Writing 1 to bit 1 of module standby register 2 stops the supply of the system clock to the A/D module and cuts the current (IAD ) flowing in the ladder resistor. Usage notes: * Use the SEM or SEMD instruction to write to the A/D start flag (ADSF). * Do not write to the ADSF during A/D conversion. * Data in the A/D data register is undetermined during A/D conversion.
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* As the A/D converter operates on a clock from OSC, it stops in stop mode, watch mode, and subactive mode. The current flowing in the A/D converter ladder resistor is also cut in these low-power modes to reduce power consumption. * When an analog input pin is selected by the A/D mode register, the pull-up MOS for that pin is disabled.
135
HD404889/HD404899/HD404878/HD404868 Series
LCD Circuit
The MCU incorporates a controller and driver that drive four common signal pins and 32 segment pins (24 segment pins in the HD404868 Series). The controller unit consists of a RAM unit that stores the display data, a display control register (LCR), and a duty/clock control register (LMR) (figures 86-1 and 86-2). The LCD circuit allows four different duties and LCD clocks to be controlled by the program, and also incorporates dual-port RAM, enabling display data to be transferred to the segment signal pins automatically without program processing. If the 32 kHz oscillator clock is designated as the LCD clock source, LCD display is also possible in watch mode in which the system clock stops.
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HD404889/HD404899/HD404878/HD404868 Series
VCC Internal LCD power supply switch
V0 V1 LCD power supply control circuit
V2
V3
LCD display control register (LCR)
COM1 Internal data bus COM2 COM3 COM4 4 Common signal output circuit Pin control
Port mode register 4 (PMR4)
SEG1 to SEG4 SEG5 to SEG8 SEG9 to SEG12 SEG13 to SEG16 SEG17 to SEG32 Data bus Clock line Signal line Note: Pin function switching circuit Segment signal output circuit
2
Display control 32 Display data Dual-port display RAM (32 digits)
2
Duty selection
Clock Selector 2 LCD display mode register (LMR)
LCD input clocks
Figure 86-1 LCD Circuit Block Diagram (HD404889/HD404899/HD404878 Series)
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HD404889/HD404899/HD404878/HD404868 Series
VCC Internal LCD power supply switch
V1 LCD power supply control circuit
V2
V3
LCD display control register (LCR)
COM1 Internal data bus COM2 COM3 COM4 4 Common signal output circuit Pin control
Port mode register 4 (PMR4)
SEG1 to SEG4 SEG5 to SEG8 SEG9 to SEG12 SEG13 to SEG16 SEG17 to SEG24 Data bus Clock line Signal line Note: Pin function switching circuit Segment signal output circuit
2
Display control 24 Display data Dual-port display RAM (24 digits)
2
Duty selection
Clock Selector 2 LCD display mode register (LMR)
LCD input clocks
Figure 86-2 LCD Circuit Block Diagram (HD404868 Series)
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HD404889/HD404899/HD404878/HD404868 Series
LCD data area and segment data: $050 to $06F (HD404889/HD404899/HD404878 Series) $050 to $067 (HD404868 Series) Figures 87-1 and 87-2 show the LCD RAM area configuration. Each bit of the storage area corresponds to one of four duties. When data is written to the area corresponding to a particular duty, it is automatically output to the segment as display data.
$050 $051 $052 $053 $054 $055 $056 $057 $058 $059 $05A $05B $05C $05D $05E $05F
bit3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 COM4
bit2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 COM3
bit1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 COM2
bit0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 COM1
$060 $061 $062 $063 $064 $065 $066 $067 $068 $069 $06A $06B $06C $06D $06E $06F
bit3 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 COM4
bit2 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 COM3
bit1 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 COM2
bit0 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 COM1
Figure 87-1 LCD RAM Area Configuration (Using Dual-Port RAM) (HD404889/HD404899/HD404878 Series)
bit3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 COM4 bit2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 COM3 bit1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 COM2 bit0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 COM1 bit3 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 COM4 bit2 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 COM3 bit1 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 COM2 bit0 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 COM1
$050 $051 $052 $053 $054 $055 $056 $057 $058 $059 $05A $05B $05C $05D $05E $05F
$060 $061 $062 $063 $064 $065 $066 $067
Figure 87-2 LCD RAM Area Configuration (Using Dual-Port RAM) (HD404868 Series)
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HD404889/HD404899/HD404878/HD404868 Series
LCD control register (LCR: $02C): The LCD control register is a 4-bit write-only register that controls LCD blanking, the on/off state of the LCD power switch, display in watch mode and subactive mode, and disconnection of the LCD power supply dividing resistor, as shown in figure 88. Individual bit in this register can be set and reset by bit manipulation instructions. * Display on/off control Off: Segment signals are in the off state, regardless of LCD RAM data. On: LCD RAM data is output as segment signals. * Built-in power switch on/off control Off: The built-in LCD power switch is off. On: The built-in LCD power switch is on. If V0 and V1 are shorted externally, V1 goes to the VCC level. * LCD display in watch mode and subactive mode Off: In watch mode and subactive mode, all common and segment pins are fixed at GND potential. The built-in LCD power switch is off. On: In watch mode and subactive mode, LCD RAM data is output as segment signals. * LCD power supply dividing resistor switch on/off control Off: The built-in LCD power supply dividing resistor is disconnected. On: The built-in LCD power supply dividing resistor is connected.
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HD404889/HD404899/HD404878/HD404868 Series
LCD control register (LCR: $02C) Bit Read/Write Initial value on reset Bit name 3 W 0 LCR3 2 W 0 LCR2 1 W 0 LCR1 0 W 0 LCR0
LCR0 0 1 LCR1 0 1 LCR2 0 1 LCR3 0 1
LCD on/off control Off On
Built-in LCD power switch on/off control Off On
Watch mode/subactive mode LCD display Off On
LCD power supply dividing resistor On Off
Figure 88 LCD Control Register (LCR)
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HD404889/HD404899/HD404878/HD404868 Series
LCD duty/clock control register (LMR: $02D): The LCD duty/clock control register is a 4-bit write-only register used to set four kinds of display duty ratio and LCD reference clock (figure 89). Table 27 shows the LCD frame frequencies for each duty setting.
LCD duty/clock control register (LMR: $02D) Bit Read/Write Initial value on reset Bit name 3 W 0 LMR3 2 W 0 LMR2 1 W 0 LMR1 0 W 0 LMR0
LMR1 0
LMR0 0 1
Duty factor 1/4 1/3 1/2 1 (static drive)
1
0 1
LMR3 0
LMR2 0 1
LCD circuit clock CL0=32.768kHz x Duty/128 CL1=32.768kHz x Duty/256 CL2=oPER x Duty/256 When TMA3 = 0, CL3 =oPER x Duty/2048 When TMA3 = 1, CL3 = 32.768 kHz x Duty/512
1
0 1
Figure 89 LCD Duty/Clock Control Register (LMR)
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HD404889/HD404899/HD404878/HD404868 Series
Table 27 LCD Frame Frequencies for Each Duty Setting
Frame Period Duty LMR3 LMR2 fosc=400kHz fosc=800kHz fosc=2.0MHz fosc=4.0MHz
Division Division Division Division Division Division Division Division by 4 by 32 by 4 by 32 by 4 by 32 by 4 by 32 0 0 1 Static 1 0 1 CL0 CL1 CL2 256Hz 128Hz 390.6Hz 48.8Hz 6.1Hz 781.3Hz 97.7Hz 97.7Hz 12.2Hz 1953Hz 244.1Hz 3906Hz 488.3Hz 244.1Hz 30.5Hz 488.3Hz 61.0Hz
CL3* 48.8Hz 64Hz
0
0 1
CL0 CL1 CL2
128Hz 64Hz 195.3Hz 24.4Hz 3.1Hz 390.6Hz 48.8Hz 48.8Hz 6.1Hz 976.6Hz 122.1Hz 1953Hz 244.1Hz 122.1Hz 15.3Hz 244.1Hz 30.5Hz
1/2 1
0 1
CL3* 24.4Hz 32Hz
0
0 1
CL0 CL1 CL2
85.3Hz 42.7Hz 130.1Hz 16.3Hz 2.0Hz 260.2Hz 32.5Hz 32.5Hz 4.1Hz 650Hz 81.3Hz 81.3Hz 10.2Hz 1301Hz 162.6Hz 162.6Hz 20.3Hz
1/3 1
0 1
CL3* 16.3Hz 21.3Hz
0
0 1
CL0 CL1 CL2
64Hz 32Hz 97.7HZ 12.2Hz 1.5Hz 195.3Hz 24.4Hz 24.4Hz 3.1Hz 488.3Hz 61.0Hz 61.0Hz 7.6Hz 976.6Hz 122.1Hz 122.1Hz 15.3Hz
1/4 1
0 1
CL3* 12.2Hz 16Hz
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HD404889/HD404899/HD404878/HD404868 Series
Port mode register 4 (PMR4: $00C): Port mode register 4 (PMR4) is a 4-bit write-only register that enables the R3 to R6 port pins to be switched to SEG1 to SEG16 pin functions in 4-port units (figure 90).
Port mode register 4 (PMR4: $00C) Bit Read/Write Initial value on reset Bit name 3 W 0 2 W 0 1 W 0 0 W 0
PMR43 PMR42 PMR41 PMR40
PMR40 0 1* PMR41 0 1* PMR42 0 1* PMR43 0 1* Note:
*
R3/SEG1 to SEG4 pin mode selection
R3 SEG1-4
R4/SEG5 to SEG8 pin mode selection
R4 SEG5-8
R5/SEG9 to SEG12 pin mode selection
R5 SEG9-12
R6/SEG13 to SEG16 pin mode selection
R6 SEG13-16
When use as a segment output pin, write its port data resister (PDR) to "0"
Figure 90 Port Mode Register 4 (PMR4: $00C)
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HD404889/HD404899/HD404878/HD404868 Series
LCD drive voltage (VLCD ): Example of LCD drive power supply wiring are shown in figures 91-1 and 91-2. The LCD drive voltage (V LCD) should be within the following range. 2.2VLCDVCC (V) If the LCD drive voltage is applied from off-chip, connect the V0 pin to VCC and turn the LCD power switch (LCD control register) off. (HD404889/HD404899/HD404878 Series) When the power supply voltage is used as the LCD drive voltage, the V0 and V1 pins should be shorted. (HD404889/HD404899/HD404878 Series)
VCC
VCC V0 V1 V2 V3 GND
1 COM1 SEG1 to SEG32 32
4-digit LCD
Static drive (power supply voltage used for VLCD) 2 COM1 COM2 SEG1 to SEG32 32 1/2 duty, 1/2 bias drive (power supply voltage used for VLCD) COM1 to COM3 SEG1 to SEG32 3
VCC
VCC V0 V1 V2 V3 GND
8-digit LCD
VCC
VLCD
VCC V0 V1 V2 V3 GND
10-digit signed LCD
32 1/3 duty, 1/3 bias drive (external power supply used for VLCD) 4
VCC
VLCD
VCC V0 V1 V2 V3 GND
COM1 to COM4 SEG1 to SEG32
16-digit LCD
32 1/4 duty, 1/3 bias drive (external power supply used for VLCD)
Figure 91-1 Examples of LCD Wiring (HD404889/HD404899/HD404878 Series)
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HD404889/HD404899/HD404878/HD404868 Series
VCC VCC V1 V2 V3 GND 1 COM1 SEG1 to SEG24 24 Static drive (power supply voltage used for VLCD) 2 COM1 COM2 SEG1 to SEG24 24 1/2 duty, 1/2 bias drive (power supply voltage used for VLCD) COM1 to COM3 SEG1 to SEG24 3 3-digit LCD
VCC VCC V1 V2 V3 GND
6-digit LCD
VCC VCC VLCD V1 V2 V3 GND
8-digit LCD
24 1/3 duty, 1/3 bias drive (external power supply used for VLCD) 4
VCC VCC VLCD V1 V2 V3 GND
COM1 to COM4 SEG1 to SEG24
12-digit LCD
24 1/4 duty, 1/3 bias drive (external power supply used for VLCD)
Figure 91-2 Examples of LCD Wiring (HD404868 Series) Large LCD panel drive: If the capacitance of the driven LCD is large, the value of the divided resistance should be reduced by dividing the resistance in parallel with the built-in divided resistor (see figures 92-1 and 92-2). As an LCD has a matrix structure, the path of the charge/discharge current flowing to the load capacitance is complicated. Moreover, the current varies depending on the illumination state, so that it is not possible to determine the resistance values simply from the LCD load capacitance. The resistance values must therefore be determined experimentally in accordance with the power consumption requirement of the equipment, including the LCD. (Adding capacitors C with a value of 0.1 to 0.3 F is also effective). A value of 1 k to 10 k is normally set for R.
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HD404889/HD404899/HD404878/HD404868 Series
V0(VCC) V1 R V2 R V3 R GND R C C C R R
V0(VCC) V1 V2 V3 GND
Figure 92-1 Large LCD Panel Drive (Using Power Supply Voltage for VLCD) (HD404889/HD404899/HD404878 Series)
V1 R V2 R V3 R GND R C C C R R
V1 V2 V3 GND
Figure 92-2 Large LCD Panel Drive (Using Power Supply Voltage for VLCD) (HD404868 Series) Usage Notes When R30/SEG1 to R60/SEG16 pins are used as segment output pins, write their port data register (PDR) to "0".
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HD404889/HD404899/HD404878/HD404868 Series
Buzzer Output Circuit
Buzzer Output Circuit Functions: The buzzer output circuit has the following functions. * Timer overflow toggle output * System clock divided clock pulse output The block diagram of the buzzer output circuit is shown in figure 93. Buzzer Output Circuit Operation * Timer overflow toggle output operation The timer overflow toggle output operation setting is made by bits 1 and 2 of the buzzer mode register (BMR) and bit 2 of port mode register 2 (PMR2). By clearing bit 2 of the buzzer mode register (BMR) to 0, selecting timer B or timer C overflow by bit 1, and setting bit 2 of port mode register 2 (PMR2) to 1, a toggle waveform is output from the BUZZ pin with overflow as the trigger. * System clock divided clock pulse output The system clock divided clock pulse output operation setting is made by bits 0 to 3 of the buzzer mode register (BMR) and bit 2 of port mode register 2 (PMR2). Bit 2 of the buzzer mode register (BMR) is set to 1, the system clock division ratio is selected by bits 0 and 1, and bit 2 of port mode register 2 (PMR2) is set to 1. Clock pulses are output by setting bit 3 of the buzzer mode register (BMR) to 1. If bit 3 of the buzzer mode register (BMR) is cleared to 0, the BUZZ pin goes low. The clock pulse width is fixed without regard to the timing set by bit 3 of the buzzer mode register (BMR), and careful coordination with software is necessary with regard to the number of output pulses. After a clock pulse modification is made, clock pulses should not be output until 4tcyc after the modifying instruction. Only a bit manipulation instruction can be used on bit 3 of the buzzer mode register (BMR). Buzzer Output Circuit Registers Buzzer output circuit operation setting is performed by the following registers. Buzzer mode register (BMR: $02E) Port mode register 2 (PMR2: $00A) Buzzer mode register (BMR: $02E): The buzzer mode register (BMR) is a 4-bit write-only register used to set toggle output by timer overflow and system clock divided clock pulse output as shown in figure 94. Bit 3 of the buzzer mode register (BMR) can only accessed by a bit manipulation instruction. The buzzer mode register (BMR) is reset to $0 by an MCU reset.
148
HD404889/HD404899/HD404878/HD404868 Series
Port mode register 2 (PMR2: $00A): Port mode register 2 (PMR2) is a 4-bit write-only register used to switch the R12/BUZZ pin function as shown in figure 30. Port mode register 2 (PMR2) is reset to $0 by an MCU reset.
BUZZ
Timer B overflow Timer C overflow
Selector
1/2 (toggle)
Selector
oPER 1/2 1/3 1/4 Selector Synchronization circuit
Data bus Clock line Signal line
Buzzer mode register
Figure 93 Buzzer Output Circuit
Internal data bus 149
HD404889/HD404899/HD404878/HD404868 Series
Buzzer mode register (BMR: $02E) Bit Read/Write Initial value on reset Bit name 3 W 0 BMR3 2 W 0 BMR2 1 W 0 BMR1 0 W 0 BMR0
BMR2 BMR1 BMR0 0 0 1 * 0 0 1 1 * : Don't care 1 0 1 *
BUZZ pin output Division by 2 of timer B overflow Division by 2 of timer C overflow oPER clock oPER/2clock oPER/3clock oPER/4clock
Clock output control (enabled when BMR2 = 1, bit manipulation instruction) 0 1 Stopped (low level) Output
Figure 94 Buzzer Mode Register (BMR)
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HD404889/HD404899/HD404878/HD404868 Series
ZTATTM Microcomputer with Built-in Programmable ROM
1. Precautions for use of ZTATTM microcomputer with built-in programmable ROM (1) Precautions for writing to programmable ROM built in ZTATTM microcomputer In the ZTAT TM microcomputer with built-in plastic mold one-time programmable ROM, incomplete electrical connection between the PROM writer and socket adapter causes writing errors and, makes the computer unoperatable. To enhance the writing efficiency, attention should be paid to the following points: (a) Make sure that the socket adapter is firmly fixed to the PROM writer and connected electrically with each other (neither opened nor shorted), before starting the writing process. (b) To secure the electrical connection between the contact pin and IC lead, make sure that there is no foreign substance on the contact pin of the socket adapter, which may cause improper electrical connection. (c) When inserting the IC, be careful to protect the IC lead from bending in order to secure the electrical connection between the contact pin and IC lead. If the lead is bent, correct the bending and insert it again. (d) If any trouble is noticed during a blank check to be performed to prevent erroneous writing due to improper electrical connection, carry out the writing process again according to above steps (a), (b), and (c). (e) During the writing process, do not touch the socket adapter and IC to prevent erroneous writing. (f) To write continuously in the IC, follow steps (a), (b), (c), (d) and (e). (g) If a writing error recurs, or the rate of writing errors occur frequently, stop writing and check the PROM writer, socket adapter, etc. for defects. (h) If any problem is noticed in the written program or in the program after being left at a high temperature, consult our technical staff. (2) Precautions when new PROM writer, socket adapter or IC is used When a new PROM writer, socket adapter or IC is employed, breakdown of the IC may occur or its writing may become impossible because the noise, overshoot, timing or other electrical characteristics may be inconsistent with the assured IC writing characteristics. To avoid such troubles, check the following points before starting the writing process. (a) To ensure stable writing operation, check that the VCC of the power supplied to the PROM writer, power source current capacity of VPP, and current consumption at the time of writing to IC are provided with sufficient margin. (b) To prevent breakdown of the IC, check that the power source voltage between GND-V CC and GNDVPP, and overshoot or undershoot of the power source at the connecting terminal of the socket adapter are within the ratings. Particularly, if the overshoot or undershoot exceeds the maximum rating, the p-n connection may be damaged, leading to permanent breakdown. If overshoot or undershoot occurs, recheck the power source damping resistance of capacity. (c) To prevent breakdown of the IC and for stable writing and reading operation, insert the IC into the socket adapter and check the power noise between the GND-VCC and GND-VPP near the IC connecting
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HD404889/HD404899/HD404878/HD404868 Series
terminal. If power source noise is noticed, insert an appropriate capacitor between the GND power sources depending on the noise generated. In case of high frequency noise , insert a capacitor of low inductance. (d) For stable writing and reading operation, insert the IC into the socket adapter and check the input waveform, timing and noise near the R/W, CS, address and data terminals. Particularly, since recent ICs have increased in speed, caution should be exercised against the noise to the power source or address due to crosstalk from the output data terminal. To avoid these problems, inserting a low inductance capacitor between the GND and power source or inserting a damping resistance to the output data terminal is effective. (e) Particularly, when a multiple PROM writer is used, perform above items (a), (b), (c), and (d) assuming all ICs inserted into the socket adapter. (f) In the case of a multiple PROM writer, when an unacceptable result is noticed during a blank check performed to prevent erroneous writing due to improper electrical connection of the power source, etc., rewriting is impossible unless every writing process can be stopped. Therefore, the potential increases due to erroneous writing because of improper connection. Be sure to check the electrical connection between the PROM writer and socket adapter and IC. (g) If any abnormality is noticed while checking a written program, consult our technical staff. 2. Programming of Built-in programmable ROM The MCU can stop its function as an MCU in PROM mode for programming the built-in PROM. PROM mode is set by driving the RESET, M0, and M1 pins low (or by driving the RESET and M0 pins low in the HD4074869), and driving the TEST pin to the VPP level. Writing and reading specifications of the PROM are the same as those for the commercial EPROM27256. Using a socket adapter for specific use of each product, programming is possible with a general-purpose PROM writer. Since an instruction of the HMCS400 series is 10 bits long, a conversion circuit is incorporated to adapt the general-purpose PROM writer. This circuit splits each instruction into five lower bits and five higher bits to write from or read to two addresses. This enables use of a general-purpose PROM. For instance, to write to a 16kword of built-in PROM writer with a general-purpose PROM, specify 32kbyte address ($0000-$7FFF). An example of PROM memory map is shown in figure 95. Notes: 1. When programming with a PROM writer, set up each ROM size to the address given in table 30. If it is programmed erroneously to an address given in table 30 or later, check of writing of PROM may become impossible. Particularly, caution should be exercised in the case of a plastic package since reprogramming is impossible with it. Set the data in unused addresses to $FF. 2. If the indexes of the PROM writer socket, socket adapter and product are not aligned precisely, the product may break down due to overcurrent. Be sure to check that they are properly set to the writer before starting the writing process.
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3. Two levels of program voltages (VPP) are available for the PROM: 12.5V and 21V. Our product employs a V PP of 12.5V. If a voltage of 21V is applied, permanent breakdown of the product will result. The VPP of 12.5V is obtained for the PROM writer by setting it according to the Intel 27258 specifications. Table 28
Package FP-80A TFP-80C FP-64A DP-64S
Socket Adapters
Model Name Please ask Hitachi service section. Please ask Hitachi service section. Please ask Hitachi service section. Please ask Hitachi service section. Manufacturer
Writing/verification
Programming of the built-in program ROM employs a high speed programming method. With this method, high speed writing is effected without voltage stress to the device or without damaging the reliability of the written data. A basic programming flow chart is shown in figure 96 and a timing chart in figure 97. For precautions for PROM writing procedure, refer to Section 2, "Characteristics of ZTATTM Microcomputer's Built-in Programmable ROM and precautions for its Applications." Table 29
Mode Writing Verification Prohibition of programming
Selection of Mode
CE "Low" "High" "High" OE "High" "Low" "High" VPP VPP VPP VPP O0 to O4 Data input Data output High impedance
Table 30
ROM size 8k 12k 16k
PROM Writer Program Address
Address $0000~$3FFF $0000~$5FFF $0000~$7FFF
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Programmable Rom (HD4074889, HD4074899, HD4074869)
The HD4074889, HD4074899, and HD4074869 are a ZTATTM microcomputers with built-in PROM that can be programmed in PROM mode. PROM Mode Pin Description HD4074889, HD4074899
Pin No. FP-80A TFP-80C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 MCU Mode Pin Name AVCC R70/AN0 R71/AN1 R72/AN2 R73/AN3 R80/AN4 R81/AN5 AVSS TEST OSC1 OSC2 GND X2 X1 RESET V CC D0/INT0 D1/INT1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 R00/WU 0 R01/WU 1 R02/WU 2 R03/WU 3 R10/EVNB R11/EVND R12/BUZZ R13/TOB R20/TOC R21/SCK R22/SI/SO R23 I/O -- I/O I/O I/O I/O I/O I/O -- I I O -- O I I -- I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PROM Mode Pin Name I/O V CC V CC V CC -- -- -- Pin No. FP-80A TFP-80C 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 MCU Mode Pin Name R30/SEG1 R31/SEG2 R32/SEG3 R33/SEG4 R40/SEG5 R41/SEG6 R42/SEG7 R43/SEG8 R50/SEG9 R51/SEG10 R52/SEG11 R53/SEG12 R60/SEG13 R61/SEG14 R62/SEG15 R63/SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 COM1 COM2 COM3 COM4 V3 V2 V1 V0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O O O -- -- -- -- PROM Mode Pin Name I/O A1 A2 A3 A4 O0 O1 O2 O3 O4 O4 O3 O2 O1 O0 I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
GND V PP V CC GND GND RESET V CC A0 A5 A6 A7 A8 A9 A 10 A 11 A 12 A 13 A 14 V CC
-- -- -- -- -- I -- I I I I I I I I I I I --
M0 M1 CE OE XM0 XM1
I I I I O O
V CC V CC
-- --
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HD4074869
Pin No. FP-64A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DP-64S 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 MCU Mode Pin Name R70/AN0 R71/AN1 R72/AN2 R73/AN3 TEST OSC1 OSC2 GND X2 X1 RESET V CC D0/INT0 D1/INT1 D2 D3 D4 D5 D6 D7 D8 D9 R00/WU 0 R01/WU 1 R02/WU 2 R10/EVNB R11 R12/BUZZ R13/TOB R20/TOC R21/SCKN R22/SI/SO I/O I/O I/O I/O I/O I I O -- O I I -- I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PROM Mode Pin Name I/O V CC -- V CC -- Pin No. FP-64A 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 DP-64S 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 MCU Mode Pin Name R23 R30/SEG1 R31/SEG2 R32/SEG3 R33/SEG4 R40/SEG5 R41/SEG6 R42/SEG7 R43/SEG8 R50/SEG9 R51/SEG10 R52/SEG11 R53/SEG12 R60/SEG13 R61/SEG14 R62/SEG15 R63/SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 COM1 COM2 COM3 COM4 V3 V2 V1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O -- -- -- PROM Mode Pin Name I/O A 14 I A1 I A2 I A3 I A4 I O0 I/O O1 I/O O2 I/O O3 I/O O4 I/O O4 I/O O3 I/O O2 I/O O1 I/O O0 I/O
V PP V CC GND GND RESET V CC A0 A5 A6 A7 A8 A9 A 10 A 11 A 12 V CC
-- -- -- -- I -- I I I I I I I I I --
A 13 M0 CE XM1 OE XM0
I I I O I O
V CC
--
Notes: 1. I/O: I/O pin, I: Input-only pin, O: Output-only pin 2. As there are two each of pins O0 to O 4, the respective pairs should be shorted. 3. Unused data pins (O 5 to O 7) on the PROM programmer side should be handled as shown below on the socket.
VCC
O5, O6, O7
4. Pin A 9 should be handled as shown below on the socket.
VCC
A9 HD4074889 HD4074899 HD4074869
Writer side
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HD404889/HD404899/HD404878/HD404868 Series
2. Pin Functions in PROM Mode VPP: Applies the on-chip PROM programming voltage (12.5 V 0.3 V). CE: Inputs a control signal to set the on-chip PROM to the write/verify enabled state. OE: Inputs a data output control signal during verification. A0 to A14: On-chip PROM address input pins. O0 to O4: On-chip PROM data bus I/O pins. As there are two each of pins O0 to O4, the respective pairs should be shorted. M0, M1, RESET, TEST: PROM mode setting pins. PROM mode is set by driving the M0, M1, and RESET pins low (or by driving the M0, and RESET pins low in the HD4074869), and driving the TEST pin to the VPP level. Other pins: VCC, AVCC, R70/AN0, R71/AN1, OSC1, V0, and V1 should be connected to VCC potential. GND, AVSS, and X1 should be connected to GND potential. Other pins should be left open.
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HD404889/HD404899/HD404878/HD404868 Series
$0000 $0001 . . . $001F $0020 . . . $007F $0080 . . . $1FFF $2000 1 1 1 1 1 1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Lower 5 bits Upper 5 bits $0000
Vector address
$000F $0010
Zero-page subroutine (64 words)
$003F $0040
Pattern (4,096 words)
$0FFF $1000
Program (16,384 words)
JMPL instruction (jump to RESET routine) JMPL instruction (jump to WU0 to WU3 JMPL instruction (jump to INT0 routine) JMPL instruction (jump to INT1 routine) JMPL instruction (jump to timer A routine) JMPL instruction (jump to timer B, timer D routine) JMPL instruction (jump to timer C routine) JMPL instruction (jump to A/D, serial routine)
$0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F
$7FFF
$3FFF
Upper three bits are not to be used (fill them with 111)
Figure 95 Memory Map in PROM Mode
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Start Set Prog./Verify Mode VPP=12.50.3V, VCC=6.00.25V Address=0 n=0 Yes n+1n No S=25 NoGo Verify Go Program tOPW = 3nms Last Address? Yes Set Read Mode VCC=5.00.5V, VPP=VCC0.6V NoGo Read All Address Go Fail End No Address + 1Address nFigure 96 Flowchart of High-Speed Programming
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Programming Electrical Characteristics DC Characteristics (V CC = 6V 0.25V, VPP = 12.5V 0.3V, V SS = 0V, T a = 25C 5C, unless otherwise specified)
Item Input high voltage Input low voltage Output high voltage Output low voltage Symbol O0 to O 4,A 0 to A 14 , VIH OE, CE O0 to O 4,A 0 to A 14 , VIL OE, CE O0 to O 4 O0 to O 4 VOH VOL I OH=-200A I OL =1.6mA Vin=5.25V/0.5V Test Conditions min 2.2 -0.3 2.4 -- -- -- -- typ -- -- -- -- -- -- -- max Unit
VCC+0.3 V 0.8 -- 0.4 2 30 40 V V V A mA mA
Input leakage current O0 to O 4,A 0 to A 14 , IIL OE, CE VCC current VPP current I CC I PP
AC Characteristics (V CC = 6V 0.25V, VPP = 12.5V 0.3V, Ta = 25C 5C, unless otherwise specified)
Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time Program pulse width CE pulse width during overprogramming VCC setup time Data output delay time Symbol t AS t OES t DS t AH t DH t DF t VPS t PW t OPW t VCS t OE See figure 89 Test Conditions min 2 2 2 0 2 -- 2 0.95 2.85 2 0 typ -- -- -- -- -- -- -- 1.0 -- -- -- max -- -- -- -- -- 130 -- 1.05 78.75 -- 500 Unit s s s s s ns s ms ms s ns
Notes: Input pulse level: 0.8 V to 2.2 V Input rise/fall times: 20ns Input timing reference levels: 1.0 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V
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HD404889/HD404899/HD404878/HD404868 Series
Write Address tAS Data tDS VPP VPP VCC tVPS Data In Stable tDH tAH Data Out Valid tDF Verify
VCC VCC GND CE
tVCS
tPW OE tOPW
tOES
tOE
Figure 97 PROM Write/Verify Timing
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HD404889/HD404899/HD404878/HD404868 Series
Notes on PROM Programming Principles of Programming/Erasure: A memory cell in a ZTATTM microcomputer is the same as an EPROM cell; it is programmed by applying a high voltage between its control gate and drain to inject hot electrons into its floating gate. These electrons are stable, surrounded by an energy barrier formed by an SiO 2 film. The change in threshold voltage of a memory cell with a charged floating gate makes the corresponding bit appear as 0; a cell whose floating gate is not charged appears as a 1 bit (figure 98). The charge in a memory cell may decrease with time. This decrease is usually due to one of the following causes: * Ultraviolet light excites electrons, allowing them to escape. This effect is the basis of the erasure principle. * Heat excites trapped electrons, allowing them to escape. * High voltages between the control gate and drain may erase electrons. If the oxide film covering a floating gate is defective, the electron erasure rate will be greater. However, electron erasure does not often occur because defective devices are detected and removed at the testing stage.
Control gate SiO2 Source N+ N+ SiO2 Floating gate Drain Source N+ N+ Floating gate Drain Control gate
Write (0)
Erasure (1)
Figure 98 Cross-Sections of a PROM Cell PROM Programming: PROM memory cells must be programmed under specific voltage and timing conditions. The higher the programming voltage VPP and the longer the programming pulse t PW is applied, the more electrons are injected into the floating gates. However, if V PP exceeds specifications, the pn junctions may be permanently damaged. Pay particular attention to overshooting in the PROM programmer. In addition, note that negative voltage noise will produce a parasitic transistor effect that may reduce breakdown voltages. The ZTATTM microcomputer is electrically connected to the PROM programmer by a socket adapter. Therefore, note the following points: * Check that the socket adapter is firmly mounted on the PROM programmer. * Do not touch the socket adapter or the LSI during the programming. Touching them may affect the quality of the contacts, which will cause programming errors.
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HD404889/HD404899/HD404878/HD404868 Series
PROM Reliability after Programming: In general, semiconductor devices retain their reliability, provided that some initial defects can be excluded. These initial defects can be detected and rejected by screening. Baking devices under high-temperature conditions is one method of screening that can rapidly eliminate data-hold defects in memory cells. (Refer to the previous Principles of Programming/Erasure section.) ZTATTM microcomputer devices are extremely reliable because they have been subjected to such a screening method during the wafer fabrication process, but Hitachi recommends that each device be exposed to 150C at one atmosphere for at least 48 hours after it is programmed, to ensure its best performance. The recommended screening procedure is shown in figure 99. Note: If programming errors occur continuously during PROM programming, suspend programming and check for problems in the PROM programmer or socket adapter. If programming verification indicates errors in programming or after high-temperature exposure, please inform Hitachi.
Programming, verification
Exposure to high temperature, without power 150C 10C, 48 h +8 h *
-0 h
Program read check VCC = 4.5 V or 5.5 V Note: Exposure time is measured from when the temperature in the heater reaches 150C.
Figure 99 Recommended Screening Procedure
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Addressing Modes
RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 100 and described below. Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions.
W register W1 W0 X3 X register X2 X1 X0 Y3 Y register Y2 Y 1 Y0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Register Indirect Addressing
1st word of Instruction Opcode d
9
2nd word of Instruction d8 d7 d6 d5 d4 d3 d2 d1 d0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Direct Addressing
Instruction Opcode 0 0 0 1 0 0 m3 m2 m1 m0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Memory Register Addressing
Figure 100 RAM Addressing Modes
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HD404889/HD404899/HD404878/HD404868 Series
ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 101 and described below. Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13-PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7-PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page, as shown in figure 103. This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-series cross assembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000- $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC5-PC0), and 0s are placed in the eight highorder bits (PC13-PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 102. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter.
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HD404889/HD404899/HD404878/HD404868 Series
[JMPL] [BRL] [CALL] 1st word of instruction Opcode p3 p2 p1 p0 d9 d8 2nd word of instruction d7 d6 d5 d4 d3 d2 d1 d0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Opcode b7 b6 b5 b4 b3 b2 b1 b0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 0 0 0 0 Opcode 0 0 0 d5 d4 d3 d2 d1 d0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction
[TBR]
Opcode
p3
p2
p1
p0 B register B3 B2 B1 B0 A3 Accumulator A2 A1 A0
0 Program counter
0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Table Data Addressing
Figure 101 ROM Addressing Modes
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HD404889/HD404899/HD404878/HD404868 Series
Instruction [P] Opcode p3 p2 p1 p0 B3 0 0 B register B2 B1 B0 A3 Accumulator A2 A1 A0
Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Accumulator, B register
B3
B2
B1
B0
A3 A
2
A1
A
0
If RO 8 = 1
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Output registers R1, R2
R23 R22 R21 R20 R13 R12 R11 R10 Pattern Output
If RO 9 = 1
Figure 102 P Instruction
256 (n - 1) + 255 BR AAA 256n
AAA
NOP
BR BR
AAA BBB
256n + 254 256n + 255 256 (n + 1)
BBB
NOP
Figure 103 Branching when the Branch Destination is on a Page Boundary
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Instruction Set
The MCU Series has 101 instructions, classified into the following 10 groups: * * * * * * * * * * Immediate instructions Register-to-register instructions RAM addressing instructions RAM register instructions Arithmetic instructions Compare instructions RAM bit manipulation instructions ROM addressing instructions Input/output instructions Control instructions
The functions of these instructions are listed in tables 31 to 40, and an opcode map is shown in table 41. Table 31 Immediate Instructions
Words/ Cycles 1/1 1/1 2/2 NZ 1/1
Operation Load A from immediate Load B from immediate Load memory from immediate Load memory from immediate, increment Y
Mnemonic LAI i LBI i LMID i,d LMIIY i
Operation Code 1 0 0 0 1 1 i3 i2 i1 i0 1 0 0 0 0 0 i3 i2 i1 i0 0 1 1 0 1 0 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 0 0 1 i3 i2 i1 i0
Function iA iB iM i M, Y + 1 Y
Status
167
HD404889/HD404899/HD404878/HD404868 Series
Table 32 Register-Register Instructions
Words/ Cycles 1/1 1/1 2/2* 1/1 1/1 1/1 1/1 1/1
Operation Load A from B Load B from A Load A from W Load A from Y Load A from SPX Load A from SPY Load A from MR Exchange MR and A
Mnemonic LAB LBA LAW LAY LASPX LASPY LAMR m XMRA m
Operation Code 0001001000 0011001000 0100000000 0000000000 0010101111 0001101000 0001011000 1 0 0 1 1 1 m3 m2 m1 m0 1 0 1 1 1 1 m3 m2 m1 m0
Function BA AB WA YA SPX A SPY A MR (m) A MR (m) A
Status
Note:
The assembler automatically provides an operand for the second word of the LAW instruction.
Table 33
RAM Address Instructions
Words/ Cycles 1/1 1/1 1/1 2/2* 1/1 1/1 NZ NB OVF NB 1/1 1/1 1/1 1/1 1/1 1/1 1/1
Operation Load W from immediate Load X from immediate Load Y from immediate Load W from A Load X from A Load Y from A Increment Y Decrement Y Add A to Y Subtract A from Y Exchange X and SPX Exchange Y and SPY Exchange X and SPX, Y and SPY
Mnemonic LWI i LXI i LYI i LWA LXA LYA IY DY AYY SYY XSPX XSPY XSPXY
Operation Code 0 0 1 1 1 1 0 0 i1 i0 1 0 0 0 1 0 i3 i2 i1 i0 1 0 0 0 0 1 i3 i2 i1 i0 0100010000 0000000000 0011101000 0011011000 0001011100 0011011111 0001010100 0011010100 0000000001 0000000010 0000000011
Function iW iX iY AW AX AY Y+1Y Y-1Y Y+AY Y-AY X SPX Y SPY X SPX,Y SPY
Status
Note: The assembler automatically provides an operand for the second word of the LWA instruction.
168
HD404889/HD404899/HD404878/HD404868 Series
Table 34 RAM Register Instructions
Words/ Cycles 1/1
Operation Load A from memory
Mnemonic LAM LAMX LAMY LAMXY
Operation Code 0010010000 0010010001 0010010010 0010010011 0110010000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0001000000 0001000001 0001000010 0001000011 0010010100 0010010101 0010010110 0010010111 0110010100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0001010000 0001010001 0011010000 0011010001
Function MA MA X SPX MA Y SPY MA X SPX, Y SPY MA MB MB X SPX MB Y SPY MB X SPX, Y SPY AM AM X SPX AM Y SPY AM X SPX, Y SPY AM A M, Y + 1 Y A M, Y + 1 Y X SPX A M, Y - 1 Y A M, Y - 1 Y X SPX
Status
Load A from memory Load B from memory
LAMD d LBM LBMX LBMY LBMXY
2/2 1/1
Load memory from A
LMA LMAX LMAY LMAXY
1/1
Load memory from A Load memory from A, increment Y
LMAD d LMAIY LMAIYX
2/2 NZ 1/1
Load memory from A, decrement Y
LMADY LMADYX
NB
1/1
169
HD404889/HD404899/HD404878/HD404868 Series
Table 34 RAM Register Instructions (cont)
Words/ Cycles 1/1
Operation Exchange memory and A
Mnemonic XMA XMAX XMAY XMAXY
Operation Code 0010000000 0010000001 0010000010 0010000011 0110000000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0011000000 0011000001 0011000010 0011000011
Function MA MA X SPX MA Y SPY MA X SPX, Y SPY MA MB MB X SPX MB Y SPY MB X SPX, Y SPY
Status
Exchange memory and A Exchange memory and B
XMAD d XMB XMBX XMBY XMBXY
2/2 1/1
170
HD404889/HD404899/HD404878/HD404868 Series
Table 35 Arithmetic Instructions
Words/ Cycles 1/1 1/1 1/1 1/1 1/1 A+1A B B 1/1 1/1 1/1 1/1 1 CA 0 CA CA M+AA M+AA M + A + CA A OVF CA M + A + CA A OVF CA M - A - CA A NB CA M - A - CA A NB CA ABA AMA AMA AMA AMA AMA AMA NZ NZ NZ NZ NZ NZ OVF OVF OVF OVF NB NB 1/1 1/1 1/1 1/1 2/2 1/1 2/2 1/1 2/2 1/1 1/1 2/2 1/1 2/2 1/1 2/2
Operation Add immediate to A Increment B Decrement B Decimal adjust for addition Decimal adjust for subtraction Negate A Complement B Rotate right A with carry Rotate left A with carry Set carry Reset carry Test carry Add A to memory Add A to memory Add A to memory with carry Add A to memory with carry Subtract A from memory with carry Subtract A from memory with carry OR A and B AND memory with A AND memory with A OR memory with A OR memory with A EOR memory with A EOR memory with A
Mnemonic AI i IB DB DAA DAS NEGA COMB ROTR ROTL SEC REC TC AM AMD d AMC AMCD d SMC SMCD d OR ANM ANMD d ORM ORMD d EORM EORMD d
Operation Code 1 0 1 0 0 0 i3 i2 i1 i0 0001001100 0011001111 0010100110 0010101010 0001100000 0101000000 0010100000 0010100001 0011101111 0011101100 0001101111 0000001000 0100001000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000011000 0100011000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0010011000 0110011000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0101000100 0010011100 0110011100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000001100 0100001100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000011100 0100011100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
Function A+iA B+1B B-1B
Status OVF NZ NB
171
HD404889/HD404899/HD404878/HD404868 Series
Table 36 Compare Instructions
Words/ Cycles 1/1 2/2 1/1 2/2 1/1 1/1 1/1 2/2 1/1 2/2 1/1 1/1
Operation Immediate not equal to memory Immediate not equal to memory A not equal to memory A not equal to memory B not equal to memory Y not equal to immediate Immediate less than or equal to memory Immediate less than or equal to memory A less than or equal to memory A less than or equal to memory B less than or equal to memory A less than or equal to immediate
Mnemonic INEM i INEMD i,d ANEM ANEMD d BNEM YNEI i ILEM i ILEMD i,d ALEM ALEMD d BLEM ALEI i
Operation Code 0 0 0 0 1 0 i3 i2 i1 i0 0 1 0 0 1 0 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000000100 0100000100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0001000100 0 0 0 1 1 1 i3 i2 i1 i0 0 0 0 0 1 1 i3 i2 i1 i0 0 1 0 0 1 1 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000010100 0100010100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0011000100 1 0 1 0 1 1 i3 i2 i1 i0
Function iM iM AM AM BM Yi iM iM AM AM BM Ai
Status NZ NZ NZ NZ NZ NZ NB NB NB NB NB NB
Table 37
Operation
Set memory bit Set memory bit
RAM Bit Manipulation Instructions
Words/ Cycles 1/1 2/2 1/1 2/2 M (n) M (n) 1/1 2/2
Mnemonic SEM n SEMD n,d REM n REMD n,d TM n TM n,d
Operation Code 0 0 1 0 0 0 0 1 n1 n0 0 1 1 0 0 0 0 1 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 0 0 1 0 n1 n0 0 1 1 0 0 0 1 0 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 0 0 1 1 n1 n0 0 1 1 0 0 0 1 1 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
Function i M (n) i M (n) 0 M (n) 0 M (n)
Status
Reset memory bit Reset memory bit Test memory bit Test memory bit
172
HD404889/HD404899/HD404878/HD404868 Series
Table 38 ROM Address Instructions
Words/ Cycles 1/1 2/2 2/2 1 1 1 1/2 2/2 1/1 1/3 1 IE, carry restored ST 1/1
Operation Branch on status 1 Long branch on status 1 Long jump unconditionally Subroutine jump on status 1 Long subroutine jump on status 1 Table branch Return from subroutine Return from interrupt
Mnemonic BR b BRL u JMPL u CAL a CALL u TBR p RTN RTNI
Operation Code 1 1 b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 1 1 1 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 1 a5 a4 a3 a2 a1 a0 0 1 0 1 1 0 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 1 1 p3 p2 p1 p0 0000010000 0000010001
Function
Status 1 1
Table 39
Input/Output Instructions
Words/ Cycles 1/1 1/1 1/1 1/1 D (Y) D (m) R (m) A R (m) B A R (m) B R (m) 1/1 1/1 1/1 1/1 1/1 1/1 1/2
Operation Set discrete I/O latch Set discrete I/O latch direct Reset discrete I/O latch Reset discrete I/O latch direct Test discrete I/O latch Test discrete I/O latch direct Load A from R-port register Load B from R-port register Load R-port register from A Load R-port register from B Pattern generation
Mnemonic SED SEDD m RED REDD m TD TDD m LAR m LBR m LRA m LRB m Pp
Operation Code 0011100100 1 0 1 1 1 0 m3 m2 m1 m0 0001100100 1 0 0 1 1 0 m3 m2 m1 m0 0011100000 1 0 1 0 1 0 m3 m2 m1 m0 1 0 0 1 0 1 m3 m2 m1 m0 1 0 0 1 0 0 m3 m2 m1 m0 1 0 1 1 0 1 m3 m2 m1 m0 1 0 1 1 0 0 m3 m2 m1 m0 0 1 1 0 1 1 p3 p2 p1 p0
Function 1 D (Y) 1 D (m) 0 D (Y) 0 D (m)
Status
173
HD404889/HD404899/HD404878/HD404868 Series
Table 40 Control Instructions
Words/ Cycles 1/1 1/1 1/1 1/1
Operation No operation Start serial Standby mode/watch mode* Stop mode/watch mode Note:
Mnemonic NOP STS SBY STOP
Operation Code 0000000000 0101001000 0101001100 0101001101
Function
Status
Only after a transition from subactive mode.
174
HD404889/HD404899/HD404878/HD404868 Series
Table 41
R8 R9 H 0 1 2 3 4 5 6 0 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 1 8 9 A B C D E F 1-word/2-cycle instruction 1-word/3-cycle instruction
TD LWI i(2) LBI i(4) LYI i(4) LXI i(4) LAI i(4) LBR m(4) LAR m(4) REDD m(4) LAMR m(4) AI i(4) LMIIY i(4) TDD m(4) ALEI i(4) LRB m(4) LRA m(4) SEDD m(4) XMRA m(4) XMB(XY) LMADY(X) BLEM SYY SED XMA(XY) LAM(XY) ROTR ROTL SEM n(2) LMA(XY) DAA TBR p(4) LBA LYA LXA REC DB DY SEC SMC DAS NEGA LBM(XY) LMAIY(X) BNEM AYY RED
Opcode Map
0 0 1
RTNI
L
2
3
4
ALEM
5
6
7
8
AM AMC
9
A
B
C
ORM EORM
D
E
F
NOP RTN
XSPX XSPY XSPXY ANEM
INEM i(4) ILEM i(4) LAB LASPY LASPX YNEI i(4) REM n(2) ANM LAY TM n(2) IB IY TC
RAM direct address instruction (2-word/2-cycle)
2-word/2-cycle instruction
175
HD404889/HD404899/HD404878/HD404868 Series
Table 41
R8 R9 H 0 1 2 3 4 5 6 0 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 1 8 9 A B C D E F 1-word/2-cycle instruction 1-word/3-cycle instruction RAM direct address instruction (2-word/2-cycle) 2-word/2-cycle instruction
BR b(8) CAL a(6) XMAD LAMD LMAD SEMD n(2) SMCD LMID i(4) P p(4) COMB OR
Opcode Map (cont)
1 0 1 2 3 4
ANEMD ALEMD
L
5
6
7
8
AMD AMCD
9
A
B
C
ORMD
EORMD
D
E
F
LAW LWA
INEMD i(4) ILEMD i(4) STS JMPL p(4) CALL p(4) BRL p(4) REMD n(2) ANMD TMD n(2) SBY STOP
176
HD404889/HD404899/HD404878/HD404868 Series
Absolute Maximum Ratings
Item Power supply voltage Programming voltage Pin voltage Allowable input current (total) Allowable output current (total) Allowable input current (per pin) Symbol VCC VPP VT l0 - l0 l0 Value -0.3 to +7.0 -0.3 to +14.0 -0.3 to VCC+0.3 100 50 4 30 Allowable output current (per pin) -l0 4 20 Operating temperature Storage temperature Topr Tstg -20 to +75 -55 to +125 Unit V V V mA mA mA mA mA mA C C 2 3 4,5 4,6 7,8 7,9 10 11 1 Notes
Notes: Permanent damage may occur if these maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to the HD4074889, HD4074899, and HD4074869 TEST (V PP ) pin. 2. The allowable input current (total) is the sum of all currents flowing from I/O pins to ground at the same time. 3. The allowable output current (total) is the sum of all currents flowing from V CC to I/O pins. 4. The allowable input current (per pin) is the maximum current allowed to flow from any one I/O pin to ground. 5. Applies to pins D 0 to D3 and R0 to R8. 6. Applies to pins D 4 to D11 . 7. The allowable output current (per pin) is the maximum current allowed to flow from VCC to any one I/O pin. 8. Applies to pins D 4 to D11 and R0 to R8. 9. Applies to pins D 0 to D3. 10. The operating temperature indicates the temperature range in which power can be supplied to the LSI (voltage Vcc shown in the electrical characteristics tables can be applied). 11. In the case of chips, the storage specification differs from that of the package products. Please consult your Hitachi sales representative for details.
177
HD404889/HD404899/HD404878/HD404868 Series
Electrical Characteristics
DC Characteristics (HD404888, HD4048812, HD404889, HD404898, HD4048912, HD404899, HD404874, HD404878, HD404864, HD404868: VCC =1.8V to 5.5V, GND=0V, Ta=-20C to +75C; HCD404889, HCD404899, HCD404878: V CC =1.8V to 5.5V, GND=0V, Ta=+75C; HD4074889, HD4074899, HD4074869: VCC=2.0V to 5.5V, GND=0V, Ta =-20C to +75C, unless otherwise specified)
Item Input high voltage Symbol Pins VIH RESET,SCK, SI, INT0,INT1, WU0 to WU3, EVNB, EVND OSC 1 Input low voltage VIL RESET,SCK, SI, INT0,INT1, WU0 to WU3, EVNB, EVND OSC 1 Output high voltage Output low voltage I/O leakage current VOH VOL | IIL| SCK,SO, BUZZ, TOB, TOC SCK,SO, BUZZ, TOB, TOC min. typ. max. Unit Test conditions Notes
0.90V CC --
VCC+0.3 V
VCC-0.3 -- -0.3 --
VCC+0.3 V 0.10V CC V
External clock operation
-0.3
--
0.3 -- 0.4 1
V V V A
External clock operation -I OH=0.3mA I OL =0.4mA Vin=0V to VCC 1
VCC-0.5 -- -- -- --
RESET,SCK, SI,INT0, -- INT1 , WU0 to WU3, EVNB, EVND, OSC 1, TOB, TOC, SO, BUZZ VCC -- -- VCC --
Active mode current dissipation
lCC1 lCC2
3.0 0.4 1.0
5.0 1.0 2.0
mA mA mA
VCC=5V, fOSC=4MHz 2 VCC=3V, f OSC=800kHz VCC=5V, f OSC=4MHz, LCD on VCC=3V, f OSC=800kHz LCD on 2 3
Standby mode lSBY1 current dissipation lSBY2
--
0.3
0.6
mA
3
Subactive mode current dissipation
lSUB
VCC (HD404888, HD4048812, HD404889, HCD404889, HD404898, HD4048912, HD404899, HCD404899, HD404874, HD404878, HCD404878, HD404864, HD404868)
--
35
60
A
VCC = 3V, LCD on, 4,5 32 kHz oscillator used
VCC (HD4074889, -- HD4074899, HD4074869)
70
120
A
4,5
178
HD404889/HD404899/HD404878/HD404868 Series
Item Symbol Pins VCC VCC VCC min. -- -- -- 1.5 typ. max. 15 5 -- -- 30 8 5 -- Unit A A A V Test Conditions VCC = 3 V, LCD on, 32 kHz oscillator used VCC = 3 V, LCD off, 32 kHz oscillator used VCC = 3 V, no 32 kHz oscillator no 32 kHz oscillator Notes 4,5 5 5 6 Watch mode lWTC1 current dissipation lWTC2 Stop mode current lSTOP dissipation Stop mode retention voltage
VSTOP VCC
Notes: 1. Excludes output buffer current. 2. Power supply current when the MCU is in the reset state and there are no I/O currents. Test Conditions MCU State Pin States * * Reset state RESET, TEST: At ground
3. Power supply current when the on-chip timers are operating and there are no I/O currents. Test Conditions MCU State * * * Pin States * * * I/O: Same as reset state Standby mode f cyc = fOSC/4 RESET: At VCC TEST: At ground D0 to D11 , R0 to R8: At VCC
4. Applies when the LCD power supply dividing resistor is connected. 5. Power supply current when there are no I/O currents. Test Conditions Pin States * * * RESET: At VCC TEST: At ground D0 to D11 , R0 to R8: At VCC
6. Voltage needed to retain RAM data.
179
HD404889/HD404899/HD404878/HD404868 Series
I/O Characteristics for Standard Pins (HD404888, HD4048812, HD404889, HD404898, HD4048912, HD404899, HD404874, HD404878, HD404864, HD404868: VCC=1.8V to 5.5V, GND=0V, Ta=-20C to +75C; HCD404889, HCD404899, HCD404878: V C C =1.8V to 5.5V, GND=0V, Ta=+75C; HD4074889, HD4074899, HD4074869: VCC =2.0V to 5.5V, GND=0V, Ta=-20C to +75C, unless otherwise specified)
Item Input high voltage Symbol VIH Pins R0 to R8 R0 to R7 Input low voltage VIL R0 to R8 R0 to R7 Output high voltage VOH R0 to R8 R0 to R7 Output low voltage VOL R0 to R8 R0 to R7 I/O leakage current | I IL | R0 to R8 R0 to R7 MOS pull-up current -I PU R0 to R8 R0 to R7 10 50 150 A VCC=3V, VIN=0V -- -- 1 A VIN=0V to VCC -- -- 0.4 V IOL =0.4mA VCC-0.5 -- -- V -I OH=0.3mA -0.3 -- 0.3VCC V min. 0.7VCC typ. max. -- VCC+0.3 Unit V Test conditions Notes 1 2 1 2 1 2 1 2 1, 3 2, 3 1 2
Notes: 1. Applies to the HD404889, HD404899, and HD404878 Series. 2. Applies to the HD404868 Series. 3. Excludes the current flowing in the output buffer.
180
HD404889/HD404899/HD404878/HD404868 Series
I/O Characteristics for High-Current Pins (HD404888, HD4048812, HD404889, HD404898, HD4048912, HD404899, HD404874, HD404878, HD404864, HD404868: V CC =1.8V to 5.5V, GND=0V, T a =-20C to +75C; HCD404889, HCD404899, HCD404878: V CC =1.8V to 5.5V, GND=0V, Ta=+75C; HD4074889, HD4074899, HD4074869: VCC =2.0V to 5.5V, GND=0V, Ta=-20C to +75C, unless otherwise specified)
Item Input high voltage Symbol VIH Pins D0 to D11 D0 to D9 Input low voltage VIL D0 to D11 D0 to D9 Output high voltage VOH D4 to D11 D4 to D9 D0 to D3 Output low voltage VOL D0 to D3 D4 to D11 D4 to D9 I/O leakage current | I IL | D0 to D11 D0 to D9 MOS pull-up current -I PU D0 to D11 D0 to D9 10 50 150 A VCC=3V, VIN=0V -- -- 1 A VCC-2.0 -- -- -- -- -- -- 0.4 2.0 V V V -I OH=10mA, VCC=4.5 to 5.5V IOL =0.4mA IOL =15mA VCC=4.5V to 5.5V VIN =0V to VCC 1 2 1, 3 2, 3 1 2 VCC-0.5 -- -- V -I OH=0.3mA -0.3 -- 0.3VCC V min. 0.7VCC typ. max. -- VCC+0.3 Unit V Test conditions Notes 1 2 1 2 1 2
Notes: 1. Applies to the HD404889, HD404899, and HD404878 Series. 2. Applies to the HD404868 Series. 3. Excludes the current flowing in the output buffer.
181
HD404889/HD404899/HD404878/HD404868 Series
LCD Circuit Characteristics (HD404888, HD4048812, HD404889, HD404898, HD4048912, HD404899, HD404874, HD404878, HD404864, HD404868: VCC =1.8V to 5.5V, GND=0V, Ta= -20C to +75C; HCD404889, HCD404899, HCD404878: V C C =1.8V to 5.5V, GND=0V, Ta=+75C; HD4074889, HD4074899, HD4074869: VCC =2.0V to 5.5V, GND=0V, Ta=-20C to +75C, unless otherwise specified)
Item Symbol Pins SEG1 to SEG32 SEG1 to SEG24 Common driver voltage VDC drop LCD power supply dividing resistance LCD voltage RW VLCD V1 COM1 to COM4 -- 50 2.2 -- 0.3 V k V Id=3 A V1=2.7 to 5.5V V1-GND 4, 5 min. -- typ. max. -- 0.6 Unit V Test conditions Id=3 A V1=2.7 to 5.5V Notes 1, 2 1, 3 1
Segment driver voltage VDS drop
300 900 -- VCC
Notes: 1. The voltage drop from power supply pins V1, V2, V3, and GND to each segment pin or each common pin. 2. Applies to the HD404889, HD404899, and HD404878 Series. 3. Applies to the HD404868 Series. 4. In the HD404889, HD404899, and HD404878 Series, when VLCD is supplied by the internal power supply, V0 and V1 should be shorted. When V LCD is supplied by an external power supply, the relationship V CC VLCD 2.2 V should be maintained. In this case, the V0 pin should be fixed at VCC. 5. In the HD404868 Series, when VLCD is supplied by an external power supply, the relationship V CC VLCD 2.2 V should be maintained.
182
HD404889/HD404899/HD404878/HD404868 Series
A/D Converter Characteristics (HD404888, HD4048812, HD404889: VCC =1.8V to 5.5V, GND=0V, T a=-20C to +75C; HCD404889: V CC =1.8V to 5.5V, GND=0V, Ta=+75C; HD4074889: VCC=2.0V to 5.5V, GND=0V, T a=-20C to +75C, unless otherwise specified)
Item Analog power supply voltage Analog input voltage AV CC-AVSS current Analog input capacitance Resolution Number of inputs Absolute accuracy Symbol AV CC AV in IAD CAin AN0 to AN5 Pins AV CC AN0 to AN5 min. VCC-0.3 AV SS -- -- -- 0 -- -- Conversion time Input impedance AN0 to AN5 65 1 typ. max. VCC -- -- 15 8 -- -- -- -- -- VCC+0.3 AV CC 500 -- -- 6 2.0 3.0 125 -- Unit V V A pF bit channel LSB LSB tcyc M VCC=AVCC=2.7V to 5.5V VCC=AVCC=1.8V to 2.7V 2 VCC=AVCC=5.0V Test conditions Notes 1
Notes: 1. Connect to the VCC pin when the A/D converter is not used. The AVCC setting ranges are 1.8 VAVCC5.5V (HD404888, HD4048812, HD404889, HCD404889) and 2.0VAVCC5.5V (HD4074889) 2. The conversion time is 125tcyc.
183
HD404889/HD404899/HD404878/HD404868 Series
(HD404898, HD4048912, HD404899: VCC=1.8V to 5.5V, GND=0V, Ta=-20C to +75C; HCD404899: VCC =1.8V to 5.5V, GND=0V, Ta=+75C; HD4074899: VCC=2.0V to 5.5V, GND=0V, Ta=-20C to +75C, unless otherwise specified)
Item Analog power supply voltage Analog input voltage AV CC-AVSS current Analog input capacitance Resolution Number of inputs Conversion time Symbol AV CC AV in IAD CAin AN0 to AN5 Pins AV CC AN0 to AN5 min. VCC-0.3 AV SS -- -- -- 0 125 65 Absolute accuracy Input impedance AN0 to AN5 -- 1 typ. max. VCC -- -- 15 10 -- -- -- -- -- VCC+0.3 AV CC 500 -- -- 6 -- 125 4.0 -- Unit V V A pF bit channel tcyc tcyc LSB M VCC = AVCC = 1.8 V to less than 2.0 V VCC=AVCC=2.0 V to 5.5V 2 VCC=AVCC=5.0V Test conditions Notes 1
Notes: 1. Connect to the VCC pin when the A/D converter is not used. The AVCC setting ranges are 1.8 VAVCC5.5V (HD404898, HD4048912, HD404899, HCD404899) and 2.0VAVCC5.5V (HD4074899) 2. Applies to HD404898, HD4048912, HD404899, and HCD404899.
(HD404864, HD404868: VCC=1.8V to 5.5V, GND=0V, Ta=-20C to +75C; HD4074869: VCC =2.0V to 5.5V, GND=0V, T a=-20C to +75C)
Item Analog input voltage Analog input capacitance Resolution Number of inputs Absolute accuracy Conversion time Symbol AV in CAin Pins AN0 to AN3 AN0 to AN3 min. GND -- -- 0 -- 125 65 Input impedance AN0 to AN3 1 typ. max. -- 15 10 -- -- -- -- -- VCC -- -- 4 4.0 -- 125 -- Unit V pF bit channel LSB tcyc tcyc M VCC = 1.8 V to less than 2.0 V VCC= 2.0 V to 5.5V 1 Test conditions Notes
Note: 1. Applies to HD404864 and HD404868.
184
HD404889/HD404899/HD404878/HD404868 Series
AC Characteristics (HD404888, HD4048812, HD404889, HD404898, HD4048912, HD404899, HD404874, HD404878, HD404864, HD404868: VCC=1.8V to 5.5V, GND=0V, Ta=-20C to +75C;, HCD404889, HCD404899, HCD404878: V CC =1.8V to 5.5V, GND=0V, Ta=+75C; HD4074889, HD4074899, HD4074869: VCC=2.0V to 5.5V, GND=0V, Ta =-20C to +75C, unless otherwise specified)
Item Clock oscillation frequency Instruction cycle time Symbol Pins fOSC OSC1, OSC2 X1,X2 tcyc tsubcyc min. typ. 0.4 -- -- max. 4.5 Unit MHz kHz s s s ms Division by 4 32 kHz oscillator used, division by 8 32 kHz oscillator used, division by 4 2 Test conditions Division by 4 Notes 1
32.768 -- 10
0.89 -- -- --
244.14 -- 122.07 -- -- 7.5
Oscillation settling tRC time(external clock and ceramic oscillator) Oscillation settling time(crystal oscillator) External clock highlevel width External clock lowlevel width tRC
OSC1, OSC2
--
OSC1, OSC2 X1,X2
-- -- 105 105 -- -- 2
-- -- -- -- -- -- --
30 2 -- -- 20 20 --
ms s ns ns ns ns tcyc /tsubcyc
VCC=2.0 to 5.5V Ta=-10 to +60C fOSC=4MHZ fOSC=4MHZ fOSC=4MHZ fOSC=4MHZ
2 2 3 3 3 3 4
tCPH tCPL
OSC1 OSC1 OSC1 OSC1 INT0 to INT1, EVNB,EVND, WU0 to WU3 INT0 to INT1, EVNB,EVND, WU0 to WU3 RESET RESET All input pins except TEST TEST
(HD404888, HD4048812, HD404889, HCD404889, HD404899, HD404898, HD4048912, HCD404899, HD404874, HD404878, HCD404878, HD404864, HD404868)
External clock rise time tCPr External clock fall time tCPf INT0 to INT1, EVNB,EVND, WU0 to WU3 high-level width INT0 to INT1, EVNB,EVND, WU0 to WU3 low-level width tIH
tIL
2
--
--
tcyc /tsubcyc
4
RESET low-level width tRSTL RESET rise time Input capacitance tRSTr Cin
2 -- -- --
-- -- -- --
-- 20 15 15
tcyc ms pF pF f=1MHz,Vin=0V
5 5
TEST (HD4074889, HD4074899, HD4074869)
--
--
40
pF
185
HD404889/HD404899/HD404878/HD404868 Series
Notes: 1. When the subsystem oscillator (32.768 kHz crystal oscillation) is used, use within the range 0.4 MHzfOSC1.0 MHz or 1.6 MHzfOSC4.5 MHz. The SSR1 bit of the system clock select register (SSR) should be set to 0 and 1, respectively. 2. The oscillation settling time is defined as follows: (1) The time required for the oscillation to settle after V CC has reached min. at power-on. (2) The time required for the oscillation to settle after RESET input has gone low when stop mode is cleared. To ensure enough time for the oscillation to settle at power-on hold the RESET input low for at least time t RC. The oscillation settling time will depend on the circuit constants and stray capacitance. The resonator should be determined in consultation with the resonator manufacturer. With regard to the system clock (OSC1, OSC 2), bits MIS1 and MIS0 in the miscellaneous register (MIS) should be set according to the oscillation settling time of the resonator used. 3. See figure 104. 4. See figure 105. 5. See figure 106.
Serial Interface Timing Characteristics (HD404888, HD4048812, HD404889, HD404898, HD4048912, HD404899, HD404874, HD404878, HD404864, HD404868: VCC=1.8V to 5.5V, GND=0V, Ta=-20C to +75C;, HCD404889, HCD404899, HCD404878: VCC =1.8V to 5.5V, GND=0V, Ta=+75C; HD4074889, HD4074899, HD4074869: VCC =2.0V to 5.5V, GND=0V, Ta=-20C to +75C, unless otherwise specified)
Item Serial clock cycle time Serial clock high-level width Serial clock low-level width Serial clock rise time Serial clock fall time Serial output data delay time Symbol tScyc tSCKH tSCKL tSC Kr tSCKf tDSO Pins SCK SCK SCK SCK SCK SO SI SI min. 1 0.4 0.4 -- -- -- 200 200 typ. max. -- -- -- -- -- -- -- -- -- -- -- 100 100 300 -- -- Unit tcyc tScyc tScyc ns ns ns ns ns Test conditions Notes
See load in figure 108 1 See load in figure 108 1 See load in figure 108 1 See load in figure 108 1 See load in figure 108 1 See load in figure 108 1 1 1
Serial input data setup tSSI time Serial input data hold time tHSI
186
HD404889/HD404899/HD404878/HD404868 Series
During Serial Clock Input
Item Serial clock cycle time Serial clock high-level width Serial clock low-level width Serial clock rise time Serial clock fall time Serial output data delay time Symbol tScyc tSCKH tSCKL tSC Kr tSCKf tDSO Pins SCK SCK SCK SCK SCK SO SI SI min. 1 0.4 0.4 -- -- -- 200 200 typ. max. -- -- -- -- -- -- -- -- -- -- -- 100 100 300 -- -- Unit tcyc tScyc tScyc ns ns ns ns ns Test conditions Notes 1 1 1 1 1 See load in figure 108 1 1 1
Serial input data setup tSSI time Serial input data hold time tHSI
Note:
1. See figure 107.
OSC1
1/fCP VCC-0.3V 0.3V tCPr tCPH tCPf
tCPL
Figure 104 External Clock Input Waveform
INT0 , INT1, EVNB, EVND, WU0 to WU3
0.9VCC 0.1VCC
tIH
tIL
Figure 105 Interrupt Timing
187
HD404889/HD404899/HD404878/HD404868 Series
RESET
0.9VCC 0.1VCC
tRSTL
tRSTr
Figure 106 Reset Timing
tScyc tSCKf SCK VCC-0.5V(0.9VCC)* 0.4V(0.1VCC)* tDOS tSCKr tSCKL tSCKH
SO
VCC-0.5V 0.4V tSSI tHSI
SI
0.9VCC 0.1VCC
Note : VCC-0.5V and 0.4V are the voltages during serial clock output. 0.9 VCC and 0.1 VCC are the voltages during serial clock input.
Figure 107 Serial Interface Timing
188
HD404889/HD404899/HD404878/HD404868 Series
VCC R1=2.6k Test point C=30pF R=12k 1S2074(H) or equivalent
Figure 108 Timing Load Circuit
189
HD404889/HD404899/HD404878/HD404868 Series
Package Dimensions
17.2 0.3
14
Unit: mm
41 40
60 61
17.2 0.3
80 1
*0.32 0.08 0.30 0.06
21 20
0.65
0.12 M 0.83
3.05 Max
*0.17 0.05 0.15 0.04
2.70
1.6
0.10 +0.15 -0.10
0 - 8
0.8 0.3
Hitachi Code JEDEC EIAJ Weight (reference value) FP-80A -- Conforms 1.2 g
0.10
*Dimension including the plating thickness Base material dimension
14.0 0.2 12 60 61 41 40
Unit: mm
14.0 0.2
80 1 *0.22 0.05 0.20 0.04 20 0.10 M 1.25
21
0.5
*0.17 0.05 0.15 0.04
1.20 Max
1.00
1.0 0 - 8 0.5 0.1
Hitachi Code JEDEC EIAJ Weight (reference value) TFP-80C -- Conforms 0.4 g
0.10
*Dimension including the plating thickness Base material dimension
190
0.10 0.10
HD404889/HD404899/HD404878/HD404868 Series
17.2 0.3
14
Unit: mm
33 32
0.8
48 49
17.2 0.3
64 1 16
17
3.05 Max
*0.17 0.05 0.15 0.04
*0.37 0.08 0.35 0.06
0.15 M
2.70
1.0
1.6 0 - 8
0.8 0.3
0.10
0.10 +0.15 -0.10
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
FP-64A -- Conforms 1.2 g
Unit: mm
64
57.6 58.5 Max
33
17.0 18.6 Max
1
1.46 Max
1.0
32
2.54 Min 5.08 Max
19.05
0.51 Min
1.78 0.25
0.48 0.10
0.25 - 0.05 0 - 15
+ 0.11
Hitachi Code JEDEC EIAJ Weight (reference value)
DP-64S -- Conforms 8.8 g
191
HD404889/HD404899/HD404878/HD404868 Series
Note on ROM Ordering
Please note the following when ordering HD404888, HD4048812, HD404898 or HD4048912 ROM. When ordering ROM, please fill the "Not used" areas below with all-1 data, to give the same amount of data as for the 16-kwords version (HD404889, HD404899). The program that converts ROM data to mask drawing data is the same as that used for the 16-kwords version, and therefore the same amount of data is necessary. This applies both to orders using EPROM and orders using data transmission.
8-kword ROM version: HD404888, HD404898 Write all-1 data to addresses $2000 to $3FFF. $0000 Vector addresses $000F $0010 Zero page subroutine area (64 words) $000F $0010 $0000
12-kword ROM version: HD4048812, HD4048912 Write all-1 data to addresses $3000 to $3FFF. Vector addresses Zero page subroutine area (64 words)
$003F $0040
$003F $0040
Program and pattern area (8,192 words) Program and pattern area (12,288 words)
$1FFF $2000
Not used
$2FFF $3000 Not used
$3FFF
$3FFF
Note : Write all-1 data in shaded areas.
192
HD404889/HD404899/HD404878/HD404868 Series
Note on ROM Ordering
Please note the following when ordering HD404874 or HD404864 ROM. When ordering ROM, please fill the "Not used" areas below with all-1 data, to give the same amount of data as for the 8-kwords version (HD404878, HD404868). The program that converts ROM data to mask drawing data is the same as that used for the 8-kwords version, and therefore the same amount of data is necessary. This applies both to orders using EPROM and orders using data transmission.
4-kword ROM version: HD404874, HD404864 Write all-1 data to addresses $1000 to $1FFF. $0000 Vector addresses $000F $0010 Zero page subroutine area (64 words)
$003F $0040
Program and pattern area (4,096 words)
$0FFF $1000
Not used
$1FFF
Note : Write all-1 data in shaded areas.
193
HD404889/HD404899/HD404878/HD404868 Series
Option List HD404888, HD4048812, HD404889, HCD404889
Please check off the appropriate applications and enter the necessary information.
Date of order Customer Department Name ROM code name LSI number (Hitachi entry) Year Month Day
1. ROM Size
u HD404888 u HD4048812 u HD404889 u HCD404889 8 kwords 12 kwords 16 kwords 16 kwords
2. Function Options
*u *u u 32 kHz CPU operation, realtime clock time base No 32 kHz CPU operation, realtime clock time base No 32 kHz CPU operation, no realtime clock time base
Note: When an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (X1 X2). 3. ROM Code Data Organization For a microcomputer with EPROM mounted (including a ZTATTM microcomputer), specify the combined upper/lower type.
u * u * Combined lower/upper type Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU... Separate lower/upper type The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively.
4. System Oscillator (OSC1-OSC2)
u u u Ceramic oscillator Crystal oscillator External clock f= f= f= MHz MHz MHz
194
HD404889/HD404899/HD404878/HD404868 Series
5. Subsystem Oscillator (X1 X2)
u u Not used Crystal resonator -- f = 32.768 kHz
6. Stop Mode
u u Yes (used) No (not used)
7. Package
u FP-80A u TFP-80C u Chip
Note: The specifications of shipped chips differ from those of the package product. Please contact our sales staff for details.
195
HD404889/HD404899/HD404878/HD404868 Series
Option List HD404898, HD4048912, HD404899, HCD404899
Please check off the appropriate applications and enter the necessary information.
Date of order Customer Department Name ROM code name LSI number (Hitachi entry) Year Month Day
1. ROM Size
u HD404898 u HD4048912 u HD404899 u HCD404899 8 kwords 12 kwords 16 kwords 16 kwords
2. Function Options
*u *u u 32 kHz CPU operation, realtime clock time base No 32 kHz CPU operation, realtime clock time base No 32 kHz CPU operation, no realtime clock time base
Note: When an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (X1 X2). 3. ROM Code Data Organization For a microcomputer with EPROM mounted (including a ZTATTM microcomputer), specify the combined upper/lower type.
u * u * Combined lower/upper type Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU... Separate lower/upper type The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively.
4. System Oscillator (OSC1-OSC2)
u u u Ceramic oscillator Crystal oscillator External clock f= f= f= MHz MHz MHz
196
HD404889/HD404899/HD404878/HD404868 Series
5. Subsystem Oscillator (X1 X2)
u u Not used Crystal resonator -- f = 32.768 kHz
6. Stop Mode
u u Yes (used) No (not used)
7. Package
u FP-80A u TFP-80C u Chip
Note: The specifications of shipped chips differ from those of the package product. Please contact our sales staff for details.
197
HD404889/HD404899/HD404878/HD404868 Series
Option List HD404874, HD404878, HCD404878
Please check off the appropriate applications and enter the necessary information.
Date of order Customer Department Name ROM code name LSI number (Hitachi entry) Year Month Day
1. ROM Size
u HD404874 u HD404878 u HCD404878 4 kwords 8 kwords 8 kwords
2. Function Options
*u *u u 32 kHz CPU operation, realtime clock time base No 32 kHz CPU operation, realtime clock time base No 32 kHz CPU operation, no realtime clock time base
Note: When an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (X1 X2). 3. ROM Code Data Organization For a microcomputer with EPROM mounted (including a ZTATTM microcomputer), specify the combined upper/lower type.
u * u * Combined lower/upper type Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU... Separate lower/upper type The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively.
4. System Oscillator (OSC1-OSC2)
u u u Ceramic oscillator Crystal oscillator External clock f= f= f= MHz MHz MHz
5. Subsystem Oscillator (X1 X2)
u u Not used Crystal resonator -- f = 32.768 kHz
6. Stop Mode
u u Yes (used) No (not used)
7. Package
u FP-80A u TFP-80C u Chip
Note: The specifications of shipped chips differ from those of the package product. Please contact our sales staff for details.
198
HD404889/HD404899/HD404878/HD404868 Series
Option List HD404864, HD404868
Please check off the appropriate applications and enter the necessary information.
Date of order Customer Department Name ROM code name LSI number (Hitachi entry) Year Month Day
1. ROM Size
u HD404864 u HD404868 4 kwords 8 kwords
2. Function Options
*u *u u 32 kHz CPU operation, realtime clock time base No 32 kHz CPU operation, realtime clock time base No 32 kHz CPU operation, no realtime clock time base
Note: When an asterisked item is selected, "crystal resonator" is necessary for subsystem oscillator (X1 X2). 3. ROM Code Data Organization For a microcomputer with EPROM mounted (including a ZTATTM microcomputer), specify the combined upper/lower type.
u * u * Combined lower/upper type Both the lower 5 data bits (L) and the upper 5 data bits (U) are written to a single EPROM in the order LULULU... Separate lower/upper type The lower 5 data bits (L) and upper 5 data bits (U) are written to separate EPROMs respectively.
4. System Oscillator (OSC1-OSC2)
u u u Ceramic oscillator Crystal oscillator External clock f= f= f= MHz MHz MHz
5. Subsystem Oscillator (X1 X2)
u u Not used Crystal resonator -- f = 32.768 kHz
6. Stop Mode
u u Yes (used) No (not used)
7. Package
u FP-64A u DP-64S
199
HD404889/HD404899/HD404878/HD404868 Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/index.htm For further information write to:
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
200

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